Patent US5371024A successfully refreshed from Google Patents.
US5371024A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device and process for manufacturing the same
Assignee: Toshiba Corp
•
Filing: 1992-09-21
•
Granted: 1994-12-06
•
Expires: 2012-09-21
Abstract
Abstract A semiconductor device has a semiconductor substrate of the first conductivity type, a gate electrode buried in a groove formed in an element region of the substrate, first source and drain regions of the second conductivity type formed in surface regions of the semiconductor substrate on either side of the gate electrode, and second source and drain regions each having a concentration higher than that of each of the first source and drain regions, the second source and drain regions being formed in the surface regions of the semiconductor substrate on either side of the gate electrode, spaced away from the gate electrode, and adjacent to the first source and drain regions, respectively. This semiconductor device has a structure wherein the gate electrode is deeply buried in the substrate. Therefore, a short channel effect can be prevented. The gate electrode buried in the groove extends through the semiconductor region, having a low impurity concentration, formed in the surface region of the semiconductor substrate, and hence two low impurity concentration regions are formed. The source and drain regions respectively consist of a low impurity concentration region and a high impurity concentration region adjacent thereto. The low impurity concentration region allows remarkable improvement of a drain breakdown voltage.
Inventors
- 👤 Katsuhiko Hieda
- 👤 Fumio Horiguchi
- 👤 Hiroshi Takato
- 👤 Fujio Masuoka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 04:09
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/601; H10D30/608; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/292; H10D62/299; H10D62/80; H10D62/83; H10D64/00; H10D64/01; H10D64/025; H10D64/027; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/512; H10D64/513; H10D64/60; H10D64/62
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
159 words
A process for manufacturing a semiconductor device comprising the steps of forming a field insulating film on a semiconductor substrate of a first conductivity type, forming an impurity region of a second conductivity type in a surface region of said semiconductor substrate isolated by said field insulating film, forming a groove which extends through said impurity region, doping an impurity of said first conductivity type in the bottom portion of said groove separated from said impurity region of a second conductivity type to an impurity concentration higher than that of said substrate, forming a gate insulating film on the inner surface of said groove, forming a gate electrode by burying a conductive material in said groove, and doping an impurity of the second conductivity type in regions, spaced apart from said gate electrode, of said impurity region to form source and drain regions, said source and drain regions having a higher impurity concentration than that of said impurity region.
Claim 2
Dependent Claim
159 words
A process for manufacturing a semiconductor device comprising the steps of forming a field insulating film on a semiconductor substrate of a first conductivity type, forming an impurity region of a second conductivity type in a surface region of said semiconductor substrate isolated by said field insulating film, forming a groove which extends through said impurity region, doping an impurity of said first conductivity type in the bottom portion of said groove separated from said impurity region of a second conductivity type to an impurity concentration higher than that of said substrate, forming a gate insulating film on the inner surface of said groove, forming a gate electrode by burying a conductive material in said groove, and doping an impurity of the second conductivity type in regions, spaced apart from said gate electrode, of said impurity region to form source and drain regions, said source and drain regions having a higher impurity concentration than that of said impurity region.
Claim 3
Dependent Claim
47 words
A process according to claim 1, wherein doping of the impurity of the second conductivity type in the regions, spaced apart from said gate electrode, of said impurity region is performed using said gate electrode, which extends on a surface of said impurity region, as a mask.
Claim 4
Dependent Claim
50 words
A process according to claim 1, wherein doping of the impurity of the second conductivity type to the regions, spaced apart from said gate electrode, of said impurity region is performed using insulating layers formed on the side walls of an upper portion of said gate electrode as a mask.
Claim 5
Dependent Claim
24 words
A process according to claim 1, wherein forming of the groove comprises etching the semiconductor substrate using a SiO 2 layer as a mask.
Claim 6
Dependent Claim
31 words
A process according to claim 1, wherein forming of the groove comprises etching the semiconductor substrate using an Si 3 N 4 layer and an SiO 2 layer as a mask.
Claim 7
Dependent Claim
69 words
A process according to claim 1, wherein doping of the impurity of the second conductivity type to the regions, spaced apart from said gate electrode, of said impurity region comprises forming a polycrystalline silicon layer on an entire surface of the substrate, doping the impurity of the second conductivity type in said polycrystalline silicon layer, and thermally diffusing the impurity from said polycrystalline silicon layer in said semiconductor substrate.
Claim 8
Dependent Claim
19 words
A process according to claim 1, wherein said field insulating film is formed by selectively oxidizing the semiconductor substrate.
Claim 9
Dependent Claim
25 words
A process according to claim 1, wherein said field insulating film is formed by burying an insulating material in a groove formed in the substrate.
Claim 10
Dependent Claim
41 words
A process according to claim 1, wherein said doping of the impurity of the second conductivity type is carried out so that a junction depth of said impurity region is substantially equal to junction depths of said source and drain regions.
Claim 11
Dependent Claim
40 words
A process according to claim 1, wherein said doping of the impurity of said second conductivity type is carried out so that a junction depth of said impurity region is larger than junction depths of said source and drain regions.
Claim 12
Dependent Claim
26 words
A process according to claim 1, wherein the impurity concentration of said substrate is in the range of 1×10 15 to 1×10 17 atoms/cm 3 .
Claim 13
Dependent Claim
35 words
A process according to claim 1, wherein an impurity concentration of a semiconductor region formed in the bottom portion of said groove is in the range of 1×10 15 to 1×10 17 atoms/cm 3 .
Claim 14
Dependent Claim
27 words
A process according to claim 1, wherein an impurity concentration of said impurity region is in the range of 1×10 18 to 1×10 20 atoms/cm 3 .
Claim 15
Dependent Claim
29 words
A process according to claim 1, wherein an impurity concentration of said source and drain region is in the range of 1×10 20 to 1×10 21 atoms/cm 3 .
Claim 16
Dependent Claim
159 words
A process for manufacturing a semiconductor device, comprising: forming a field insulating film on a semiconductor substrate of a first conductivity type; forming a first impurity region of a second conductivity type in a surface region of said semiconductor substrate isolated by said field insulating film; forming a groove extending through said first impurity region; forming a second impurity region of said first conductivity type in a bottom portion of said groove separated from said first impurity region and having an impurity concentration higher than that of said substrate; forming a gate insulating film on an inner surface of said groove; forming a gate electrode by burying a conductive material in said groove; and doping an impurity of said second conductivity type in regions, spaced apart from said gate insulating film, of said first impurity region to form source and drain regions, said source and drain regions having a higher impurity concentration than that of said first impurity region.
Claim 17
Dependent Claim
159 words
A process for manufacturing a semiconductor device, comprising: forming a field insulating film on a semiconductor substrate of a first conductivity type; forming a first impurity region of a second conductivity type in a surface region of said semiconductor substrate isolated by said field insulating film; forming a groove extending through said first impurity region; forming a second impurity region of said first conductivity type in a bottom portion of said groove separated from said first impurity region and having an impurity concentration higher than that of said substrate; forming a gate insulating film on an inner surface of said groove; forming a gate electrode by burying a conductive material in said groove; and doping an impurity of said second conductivity type in regions, spaced apart from said gate insulating film, of said first impurity region to form source and drain regions, said source and drain regions having a higher impurity concentration than that of said first impurity region.
Claim 18
Dependent Claim
57 words
A process according to claim 15, wherein said step of doping an impurity of the second conductivity type in regions, spaced apart from said gate electrode, comprises forming a third impurity region having a higher doping concentration than said first impurity region and separated from said gate insulating film by a portion of said first impurity region.
Claim 19
Dependent Claim
38 words
A process according to claim 15, wherein said step of doping an impurity region of the second conductivity type in regions, spaced apart from said gate electrode is performed subsequent to said step of forming said gate electrode.
Claim 20
Dependent Claim
98 words
A process according to claim 15, wherein: the impurity concentration of said substrate is in the range of 1×10 15 to 1×10 17 atoms/cm 3 ; an impurity concentration of a semiconductor region formed in the bottom portion of said groove is in the range of 1×10 15 to 1×10 17 atoms/cm 3 ; an impurity concentration of said first impurity region is in the range of 1×10 18 to 1×10 20 atoms/cm 3 ; and an impurity concentration of said source and drain region is in the range of 1×10 20 to 1×10 21 atoms/cm 3 .
Claim 21
Dependent Claim
49 words
A process according to claim 15, wherein said steps of forming said first impurity region, forming said groove, and forming said gate insulating film comprise forming said groove after forming said first impurity region such that said first impurity region extends only along a sidewall portion of said groove.
Claim 22
Dependent Claim
97 words
A process according to claim 1, wherein: an impurity concentration of said substrate is in the range of 1×10 15 to 1×10 17 atoms/cm 3 ; an impurity concentration of a semiconductor region formed in the bottom portion of said groove is in the range of 1×10 15 to 1×10 17 atoms/cm 3 ; an impurity concentration of said impurity region is in the range of 1×10 18 to 1×10 20 atoms/cm 3 ; and an impurity concentration of said source and drain region is in the range of 1×10 20 to 1×10 21 atoms/cm 3 .
Claim 23
Dependent Claim
39 words
A process according to claim 1, comprising doping an impurity of said first conductivity type in the bottom portion of said groove separated from said impurity region of a second conductivity type by a portion of said semiconductor substrate.
Claim 24
Dependent Claim
37 words
A process according to claim 15, comprising forming said second impurity region of said first conductivity type in said bottom portion of said groove separated from said first impurity region by a portion of said semiconductor substrate.
References Cited (Backward Citations)
DE2545871A1
Cited
JPS52115663A
Cited
US4243997A
Cited
DE2724165A1
Cited
US4329706A
Cited
DE3228588A1
Cited
DE3426306A1
Cited
US4714951A
Cited
JPS60229374A
Cited
JPS61187273A
Cited
EP0239250A2
Cited
JPS6344770A
Cited
JPS64764A
Cited
JPS64765A
Cited
JPS6437055A
Cited
US4945070A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-12-05 | 1998-06-06 | 1998-12-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-05 | 2002-06-06 | 2002-12-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-05 | 2006-06-06 | 2006-12-06 | $7700.00 | Window Closed / Lapsed |