EP0239250A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Short channel MOS transistor
Assignee: Toshiba Corp
•
Filing: 1987-02-25
•
Granted: —
•
Expires: 2007-02-25
Abstract
Abstract An MOS semiconductor device comprising a semiconductor substrate (11) and an element region (13) in the semiconductor substrate (11) which is separated from other regions by a field insulation layer (12). A MOSFET transistor has a pair of impurity diffusion regions, which are separated from one another in the semiconductor substrate (11) and constitute source and drain regions (14, 15) separated by a channel region (20), and a gate electrode (23) constituted by a stack structure consisting of a gate insulation layer (21) and a gate electrode conductor (22). The length of the gate electrode (23) in the vicinity of a central portion of a channel region (20) is shorter than the length of the gate electrode (23) at the channel region (20) portions bounding the field insulation layer (12).
Inventors
- 👤 Shigeru C/O Patent Division Toshiba Morita
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 11:09
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D30/00; H10D30/60; H10D30/601; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/519
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
143 words
An MOS semiconductor device comprising: a semiconductor substrate (11); and a MOS transistor having a pair of impurity diffusion regions which are separated from one another in the semiconductor substrate (11) and constitute source and drain regions (14, 15) separated by a channel region (20), and a gate electrode (23) constituted by a stack structure consisting of a gate insulation layer (21) and a gate conductive layer (22), the MOS transistor being surrounded by an element separating region (12); characterised in that the lengths of the gate electrode (23) and the channel region (20) between the source and drain regions (14, 15) in the vicinity of a central portion of a channel region (20) are shorter than the lengths of the gate electrode (23) and in the channel region (20) in the vicinities of channel region (20) bounding the element separation region (12).
Claim 2
Dependent Claim
143 words
An MOS semiconductor device comprising: a semiconductor substrate (11); and a MOS transistor having a pair of impurity diffusion regions which are separated from one another in the semiconductor substrate (11) and constitute source and drain regions (14, 15) separated by a channel region (20), and a gate electrode (23) constituted by a stack structure consisting of a gate insulation layer (21) and a gate conductive layer (22), the MOS transistor being surrounded by an element separating region (12); characterised in that the lengths of the gate electrode (23) and the channel region (20) between the source and drain regions (14, 15) in the vicinity of a central portion of a channel region (20) are shorter than the lengths of the gate electrode (23) and in the channel region (20) in the vicinities of channel region (20) bounding the element separation region (12).
Claim 3
Dependent Claim
52 words
An MOS semiconductor device as claimed in claim 1, characterised in that at least the drain region (15) of the MOS transistor is constituted by first and second impurity diffusion regions of relatively high and low impurity concentrations resepctively and the second impurity diffusion region is formed adjacent the channel region (20).
Claim 4
Dependent Claim
42 words
An MOS semiconductor device as claimed in claim 1 or claim 2 characterised in that a portion of the gate electrode (23) in the vicinity of the central portion of the channel region (20) facing the drain region (15) is cut away.
Claim 5
Dependent Claim
31 words
An MOS semiconductor device as claimed in claim 3 characterised in that the removed portion (23a) has a constant length in the direction between the source and drain regions (14, 15).
Claim 6
Dependent Claim
19 words
An MOS semiconductor device as claimed in claim 3 characterised in that removed portion (23b) has an arcuate edge.
Claim 7
Dependent Claim
29 words
An MOS semiconductor device as claimed in claim 5 characterised in that the arcuate edge has its centre (35) on a central axis (35) of the channel region (20).
Claim 8
Dependent Claim
75 words
An MOS semiconductor device as claimed in any of claims 1 to 6 characterised in that the ratio of the lengths of the gate electrode (23) and the channel region (20) in the vicinity of the central portion of the channel region (20) to the lengths of the gate electrode (23) and the channel region (20) in the vicinity of the channel region (20) bounding the element separation region (12) is approximately 9 to 10.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.