Patent US5369606A successfully refreshed from Google Patents.
US5369606A
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Reduced state fir filter
Assignee: Harris Corp
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Filing: 1992-09-14
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Granted: 1994-11-29
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Expires: 2012-09-14
Abstract
Abstract A method and apparatus for increasing the throughput of a finite impulse response (FIR) digital filter with particular applicability to systems in which the input signal sample values are constrained relative to the output signal. The method and apparatus include relatively constrained input data and positional information for identifying the location of the precomputed values of the state of the filter. A lookup table stores all the states of the filter (i.e., the sums of the products of signal sample values times filter weighting coefficients).
Inventors
- 👤 Clifford Hessel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 23:34
CPC Classifications
H; H03; H03H; H03H17/00; H03H17/02; H03H17/06; H03H17/0607; H03H17/0223; H03H17/0225; H03H17/0226; H03H17/0621
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
105 words
In a method of filtering an input signal in a finite impulse response (FIR) filter having plural taps in which states of the filter are stored in a memory, the improvement comprising the steps of: providing a time-varying input signal; sampling the input signal at a first rate to obtain a time-varying digital signal; addressing the memory using an address derived from the digital signal and from a position indicator signal; extracting at a second rate as the filter output, the states stored at said addressed memory; wherein the position indicator signal is related to the ratio of the second rate to the first rate.
Claim 2
Dependent Claim
105 words
In a method of filtering an input signal in a finite impulse response (FIR) filter having plural taps in which states of the filter are stored in a memory, the improvement comprising the steps of: providing a time-varying input signal; sampling the input signal at a first rate to obtain a time-varying digital signal; addressing the memory using an address derived from the digital signal and from a position indicator signal; extracting at a second rate as the filter output, the states stored at said addressed memory; wherein the position indicator signal is related to the ratio of the second rate to the first rate.
Claim 3
Dependent Claim
11 words
The method of claim 1 where the input signal is binary.
Claim 4
Dependent Claim
12 words
The method of claim 1 where the input signal has plural values.
Claim 5
Dependent Claim
17 words
The method of claim 1 wherein a field programmable gate array is used to address the memory.
Claim 6
Dependent Claim
12 words
The method of claim 4 wherein a receiver provides said input signal.
Claim 7
Dependent Claim
133 words
In a finite impulse response (FIR) filter having M taps in which states of the filter are stored in a memory that can be addressed to provide an output signal, the improvement comprising: means for receiving input signals for a FIR filter that are constrained to predetermined patterns of input data so that no more than X N of the states of the filter need be stored in the memory, where N is less than M and where X is the number of values the input signals may take; and means for addressing the states of the filter in the memory using an N bit signal that includes bits in one of the predetermined patterns and bits of positional information that describe the position of said one predetermined pattern within said input signal.
Claim 8
Dependent Claim
133 words
In a finite impulse response (FIR) filter having M taps in which states of the filter are stored in a memory that can be addressed to provide an output signal, the improvement comprising: means for receiving input signals for a FIR filter that are constrained to predetermined patterns of input data so that no more than X N of the states of the filter need be stored in the memory, where N is less than M and where X is the number of values the input signals may take; and means for addressing the states of the filter in the memory using an N bit signal that includes bits in one of the predetermined patterns and bits of positional information that describe the position of said one predetermined pattern within said input signal.
Claim 9
Dependent Claim
17 words
The FIR filter of claim 6 wherein said means for addressing comprises a field programmable gate array.
Claim 10
Dependent Claim
53 words
The FIR filter of claim 6 wherein said means for addressing comprises a shift register for providing the bits in one of the predetermined patterns and a counter for providing the bits of positional information, the bits from the shift register and the counter being combined to form an address for the memory.
Claim 11
Dependent Claim
119 words
A finite impulse response (FIR) filter receiving an input signal carrying data and having a memory for storing states of the filter, comprising: an address device that addresses the memory with an N bit address signal comprising P bits of a pattern of the data from the input signal sampled at a first periodic rate and N-P bits of pattern position data that describe the position of the pattern of data in the input signal, N being greater than P; and a circuit that takes an output signal from the memory at a second periodic rate, wherein the number of pattern position data bits is related to the ratio between the first periodic rate and the second periodic rate.
Claim 12
Dependent Claim
119 words
A finite impulse response (FIR) filter receiving an input signal carrying data and having a memory for storing states of the filter, comprising: an address device that addresses the memory with an N bit address signal comprising P bits of a pattern of the data from the input signal sampled at a first periodic rate and N-P bits of pattern position data that describe the position of the pattern of data in the input signal, N being greater than P; and a circuit that takes an output signal from the memory at a second periodic rate, wherein the number of pattern position data bits is related to the ratio between the first periodic rate and the second periodic rate.
Claim 13
Dependent Claim
17 words
The filter of claim 9 wherein said filter has M taps and N is less than M.
Claim 14
Dependent Claim
11 words
The filter of claim 9 wherein said input signal is binary.
Claim 15
Dependent Claim
51 words
The filter of claim 6 wherein said address device comprises a shift register for providing the bits of the patterns of data and a counter for providing the bits of pattern position data, the bits from the shift register and the counter being combined to form an address for the memory.
Claim 16
Dependent Claim
15 words
The filter of claim 9 wherein said address device comprises a field programmable gate array.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-28 | 1998-05-30 | 1998-11-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-28 | 2002-05-30 | 2002-11-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-28 | 2006-05-30 | 2006-11-29 | $7700.00 | Window Closed / Lapsed |