US4953184A
Expired / Lapsed
US
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Complex bandpass digital filter
Assignee: Motorola Solutions Inc
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Filing: 1989-06-01
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Granted: 1990-08-28
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Expires: 2009-06-01
Abstract
Abstract An improved complex bandpass digital filter is disclosed. According to the invention, a complex bandpass digital filter having symmetric complex coefficients is implemented using a ROM look-up table. In operation, an input bit stream is latched at a desired decimation rate and the resulting latched bits are then used to address a ROM according to the following two-cycle process: First, the bits are applied in nomal order to the ROM to obtain the real (in phase) portion of the filter output. Second, the bits are bit-reversed and then applied to the same ROM to obtain the imaginary (quadrature) portion of the filter output. Thus, complex outputs are obtained as a time-multiplexed stream from one ROM, resulting in reduced ROM storage capacity requirements.
Inventors
- 👤 Daniel A. Simone
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:35
CPC Classifications
H; H03; H03H; H03H17/00; H03H17/02; H03H17/06; H03H17/0607; H03H17/0223; H03H17/0225; H03H17/0226; H03H17/0248; H03H17/0264
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
279 words
A radio including a front end, said front end having means responsive to a received signal for providing a digital bit stream comprising a desired signal at an IF frequency, f IF , and for coupling said digital bit stream to a bandpass digital filter having a complex response symmetric about said f IF , said digital filter comprising: means for providing said digital bit stream to a shaft register at a sampling frequency, f s , said f s being a multiple of f IF , said shift register having latching means for providing a filter input comprising k bit signals, IN o -IN k-1 , to an address circuit at a rate of f s /n, where n=a decimation rate; said address circuit having means, responsive to said filter input, for providing at least a normal filter address and a reversed filter address to a read-only memory, said normal filter address comprising at least k bit signals, NOR 0 -NOR k-1 , so that NOR 0 =IN 0 , NOR 1 =IN 1 , . . . , and NOR k-1 =IN k-1 ; said reversed filter address comprising at least k bit signals, REV 0 -REV k-1 , so that REV 0 =IN k-1 , REV 1 =IN k-2 , . . . , and REV k-1 =IN 0 ; said read-only memory having means, responsive to said normal filter address, for providing a real, or in-phase, digital filter output comprising m bit signals, REAL o -REAL m-1 , and having means, responsive to said reversed filter address, for providing an imaginary, or quadrature, digital filter output comprising m bit signals, IMAG o -IMAG m-1 .
Claim 2
Dependent Claim
279 words
A radio including a front end, said front end having means responsive to a received signal for providing a digital bit stream comprising a desired signal at an IF frequency, f IF , and for coupling said digital bit stream to a bandpass digital filter having a complex response symmetric about said f IF , said digital filter comprising: means for providing said digital bit stream to a shaft register at a sampling frequency, f s , said f s being a multiple of f IF , said shift register having latching means for providing a filter input comprising k bit signals, IN o -IN k-1 , to an address circuit at a rate of f s /n, where n=a decimation rate; said address circuit having means, responsive to said filter input, for providing at least a normal filter address and a reversed filter address to a read-only memory, said normal filter address comprising at least k bit signals, NOR 0 -NOR k-1 , so that NOR 0 =IN 0 , NOR 1 =IN 1 , . . . , and NOR k-1 =IN k-1 ; said reversed filter address comprising at least k bit signals, REV 0 -REV k-1 , so that REV 0 =IN k-1 , REV 1 =IN k-2 , . . . , and REV k-1 =IN 0 ; said read-only memory having means, responsive to said normal filter address, for providing a real, or in-phase, digital filter output comprising m bit signals, REAL o -REAL m-1 , and having means, responsive to said reversed filter address, for providing an imaginary, or quadrature, digital filter output comprising m bit signals, IMAG o -IMAG m-1 .
Claim 3
Dependent Claim
39 words
The radio of claim 1 wherein said address circuit includes means for providing said normal filter address at a rate equal to f s /n and also said reversed filter address at a rate equal to f s /n.
Claim 4
Dependent Claim
34 words
The radio of claim 2 wherein said address circuit includes means for providing said normal filter address and said reversed filter address in a time-interleaved stream at a rate equal to 2f s /n.
Claim 5
Dependent Claim
7 words
The radio of claim 3 wherein n=8.
Claim 6
Dependent Claim
10 words
The radio of claim 4 wherein f IF =450 KHz.
Claim 7
Dependent Claim
10 words
The radio of claim 5 wherein f s =14.4 MHz.
Claim 8
Dependent Claim
7 words
The radio of claim 6 wherein k=22.
Claim 9
Dependent Claim
7 words
The radio of claim 7 wherein m=19.
Claim 10
Dependent Claim
17 words
The radio of claim 1 wherein said front end includes a sigma-delta Analog to Digital (A/D) converter.
Claim 11
Dependent Claim
24 words
The radio of claim 1 wherein said read-only memory is divided into several sub- read-only memories whose outputs are combined by an adder tree.
Claim 12
Dependent Claim
256 words
A bandpass digital filter having a comlex response symmetric about an IF frequency, f IF , said digital filter comprising: means for receiving a digital bit stream comprising a desired signal at said f IF , means for providing said digital bit stream to a shift register at a sampling frequency, f s , said f s being a multiple of f IF , said shift register having latching means for providing a filter input comprising k bit signals, IN o -IN k-1 , to an address circuit at a rate of f s /n, where n=a decimation rate; said address circuit having means, responsive to said filter input, for providing at least a normal filter address and a reversed filter address to a read-only memory, said normal filter address comprising at least k bit signals, NOR 0 -NOR k-1 , so that NOR 0 =IN 0 , NOR 1 =IN 1 , . . . , and NOR k-1 =IN k-1 ; said reversed filter address comprising at least k bit signals, REV 0 -REV k-1 , so that REV 0 =IN k-1 , REV 1 =IN k-2 , . . . , and REV k-1 =IN 0 ; said read-only memory having means, responsive to said normal filter address, for providing a real, or in-phase, digital filter output comprising m bit signals, REAL o -REAL m-1 , and having means, responsive to said reversed filter address, for providing an imaginary, or quadrature, digital filter output comprising m bit signals, IMAG o -IMAG m-1 .
Claim 13
Dependent Claim
256 words
A bandpass digital filter having a comlex response symmetric about an IF frequency, f IF , said digital filter comprising: means for receiving a digital bit stream comprising a desired signal at said f IF , means for providing said digital bit stream to a shift register at a sampling frequency, f s , said f s being a multiple of f IF , said shift register having latching means for providing a filter input comprising k bit signals, IN o -IN k-1 , to an address circuit at a rate of f s /n, where n=a decimation rate; said address circuit having means, responsive to said filter input, for providing at least a normal filter address and a reversed filter address to a read-only memory, said normal filter address comprising at least k bit signals, NOR 0 -NOR k-1 , so that NOR 0 =IN 0 , NOR 1 =IN 1 , . . . , and NOR k-1 =IN k-1 ; said reversed filter address comprising at least k bit signals, REV 0 -REV k-1 , so that REV 0 =IN k-1 , REV 1 =IN k-2 , . . . , and REV k-1 =IN 0 ; said read-only memory having means, responsive to said normal filter address, for providing a real, or in-phase, digital filter output comprising m bit signals, REAL o -REAL m-1 , and having means, responsive to said reversed filter address, for providing an imaginary, or quadrature, digital filter output comprising m bit signals, IMAG o -IMAG m-1 .
Claim 14
Dependent Claim
36 words
The digital filter of claim 11 wherein said address circuit includes means for providing said normal filter address at a rate equal to f s /n and also said reversed filter address at a like rate.
Claim 15
Dependent Claim
35 words
The digital filter of claim 12 wherein said address circuit includes means for providing said normal filter address and said reversed filter address in a time-interleaved stream at a rate equal to 2f s /n.
Claim 16
Dependent Claim
8 words
The digital filter of claim 13 wherein n=8.
Claim 17
Dependent Claim
11 words
The digital filter of claim 14 wherein f IF =450 KHz.
Claim 18
Dependent Claim
11 words
The digital filter of claim 15 wherein f s =14.4 MHz.
Claim 19
Dependent Claim
8 words
The digital filter of claim 16 wherein k=22.
Claim 20
Dependent Claim
8 words
The digital filter of claim 17 wherein m=19.
Claim 21
Dependent Claim
18 words
The digital filter of claim 11 wherein said receiving means includes a sigma-delta Analog to Digital (A/D) converter.
Claim 22
Dependent Claim
25 words
The digital filter of claim 11 wherein said read-only memory is divided into several sub- read-only memories whose outputs are combined by an adder tree.
References Cited (Backward Citations)
US4691292A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-27 | 1994-02-26 | 1994-08-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-27 | 1998-02-26 | 1998-08-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-27 | 2002-02-26 | 2002-08-28 | $7700.00 | Window Closed / Lapsed |