US5369045A
Expired / Lapsed
US
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Method for forming a self-aligned lateral DMOS transistor
Assignee: Texas Instruments Inc
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Filing: 1993-07-01
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Granted: 1994-11-29
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Expires: 2013-07-01
Abstract
Abstract A method of forming a LDMOS transistor device 10 is disclosed herein. A semiconductor layer 14 is provided. The layer 14 may be an n-type RESURF region formed over a p-substrate 12. An insulating layer 24, such as a field oxide, is formed on the semiconductor layer 14. The insulating layer 24 is then patterned to expose source and drain windows. A D-well region 20 is then formed within the source window portion of the semiconductor layer. A sidewall region is formed adjacent a sidewall of the insulating layer around the source window. The source and drain regions 16 and 18 are then formed, for example by implanting arsenic or phosphorus ions. A gate electrode 26 is formed over a portion of the D-well region 20 between the source region 16 and the insulating layer 24. The gate electrode 26 is formed over a channel region within the D-well 20 between the source 16 and drain 18.
Inventors
- 👤 Wia T. Ng
- 👤 Oh-Kyong Kwon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 11:45
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/028; H10D30/0281; H10D30/60; H10D30/601; H10D30/603; H10D30/64; H10D30/65; H10D62/00; H10D62/10; H10D62/17; H10D62/393; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10D64/516; Y; Y10; Y10S; Y10S148/00; Y10S148/126
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
151 words
A method of forming a DMOS transistor device comprising the steps of: providing a semiconductor layer of a first conductivity type; forming an insulating layer on said semiconductor layer; patterning said insulating layer to expose a source window portion of said semiconductor layer and to expose a drain window portion of said semiconductor layer; forming a D-well region by introducing a conductive impurity within said source window portion of said semiconductor layer; forming a sidewall region adjacent a sidewall of said insulating layer around said source window; forming a source region within said source window portion of said semiconductor layer and forming a drain region within said drain window portion of said semiconductor layer; and forming a gate electrode over a portion of said D-well region between said source region and said insulating layer, said gate electrode formed over a channel region within said D-well between said source and drain regions.
Claim 2
Independent Claim
151 words
A method of forming a DMOS transistor device comprising the steps of: providing a semiconductor layer of a first conductivity type; forming an insulating layer on said semiconductor layer; patterning said insulating layer to expose a source window portion of said semiconductor layer and to expose a drain window portion of said semiconductor layer; forming a D-well region by introducing a conductive impurity within said source window portion of said semiconductor layer; forming a sidewall region adjacent a sidewall of said insulating layer around said source window; forming a source region within said source window portion of said semiconductor layer and forming a drain region within said drain window portion of said semiconductor layer; and forming a gate electrode over a portion of said D-well region between said source region and said insulating layer, said gate electrode formed over a channel region within said D-well between said source and drain regions.
Claim 3
Dependent Claim
19 words
The method of claim 1 wherein said semiconductor layer of said first conductivity type comprises an n-doped silicon layer.
Claim 4
Dependent Claim
17 words
The method of claim 1 wherein said semiconductor layer comprises an n-type layer formed over a p-substrate.
Claim 5
Dependent Claim
13 words
The method of claim 1 wherein said insulating layer comprises a field oxide.
Claim 6
Dependent Claim
23 words
The method of claim 4 wherein said substrate is silicon and said step of forming the field oxide comprises thermally growing silicon dioxide.
Claim 7
Dependent Claim
19 words
The method of claim 1 wherein said step of patterning said insulating layer is performed with a single mask.
Claim 8
Dependent Claim
20 words
The method of claim 1 wherein said step of forming a D-well comprises implanting conductive impurities into said semiconductor layer.
Claim 9
Dependent Claim
11 words
The method of claim 7 wherein said conductive impurities comprise boron.
Claim 10
Dependent Claim
31 words
The method of claim 1 wherein said step of forming a sidewall region further comprises forming a second sidewall region adjacent a sidewall of said insulating layer around said drain window.
Claim 11
Independent Claim
31 words
The method of claim I and further comprising the step of forming a thin insulating layer over said insulating layer and said source and drain windows prior to forming said sidewalls.
Claim 12
Dependent Claim
25 words
The method of claim 10 wherein said thin insulating layer comprises a nitride layer and said insulating layer and said sidewall region comprise oxide regions.
Claim 13
Dependent Claim
13 words
The method of claim 1 wherein said sidewall region is formed from tetraethoxysilane.
Claim 14
Dependent Claim
18 words
The method of claim 1 wherein said step of forming source and drain regions comprise implanting n-type impurities.
Claim 15
Dependent Claim
14 words
The method of claim 13 wherein said n-type impurities comprise arsenic or phosphorus ions.
Claim 16
Dependent Claim
12 words
The method of claim 1 wherein said gate electrode comprises doped silicon.
Claim 17
Dependent Claim
16 words
The method of claim 1 wherein said step of forming a gate electrode comprises depositing silicon.
Claim 18
Dependent Claim
13 words
The method of claim 1 wherein said gate electrode is in situ doped.
Claim 19
Dependent Claim
28 words
The method of claim 1 and further comprising the steps of forming a source contact over said source region and forming a drain contact over said drain region.
Claim 20
Dependent Claim
23 words
The method of claim 1 and further comprising the step of forming a body contact region within said D-well adjacent said source region.
Claim 21
Independent Claim
179 words
A method of forming a lateral DMOS transistor device comprising the steps of: providing an n-type silicon layer formed over a p-type substrate; forming a field oxide layer over said n-type layer; patterning said field oxide layer to expose a source window portion of said semiconductor layer and to expose a drain window portion of said semiconductor layer; implanting boron within said source window portion of said n-type layer to form a p-type D-well; forming a nitride layer over said field oxide and source and drain windows; subsequently forming a sidewall oxide region adjacent a sidewall of said field oxide around said source window; subsequently implanting n-type impurities to form a source region within said source window portion of said silicon layer and a drain region within said drain window portion of said silicon layer, said source region formed within said D-well; and forming a gate electrode over a portion of said D-well region between said source region and said field oxide, said gate electrode formed over a channel region within said D-well between said source and drain regions.
Claim 22
Independent Claim
179 words
A method of forming a lateral DMOS transistor device comprising the steps of: providing an n-type silicon layer formed over a p-type substrate; forming a field oxide layer over said n-type layer; patterning said field oxide layer to expose a source window portion of said semiconductor layer and to expose a drain window portion of said semiconductor layer; implanting boron within said source window portion of said n-type layer to form a p-type D-well; forming a nitride layer over said field oxide and source and drain windows; subsequently forming a sidewall oxide region adjacent a sidewall of said field oxide around said source window; subsequently implanting n-type impurities to form a source region within said source window portion of said silicon layer and a drain region within said drain window portion of said silicon layer, said source region formed within said D-well; and forming a gate electrode over a portion of said D-well region between said source region and said field oxide, said gate electrode formed over a channel region within said D-well between said source and drain regions.
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| 3.5 Years (Year 4) | 1997-11-28 | 1998-05-30 | 1998-11-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-28 | 2002-05-30 | 2002-11-29 | $3760.00 | Window Closed / Lapsed |
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