Power MOS transistor structure

Claim 2

A structure of a power MOS transistor comprising a plurality of transistor cells connected in parallel, each of which comprises on a common face of a substrate gate, source and drain contact zones and three levels of connection layers, a first level of said connection layers establishing a contact with all the gates and a connection between each gate and the adjacent gates, this first level of said connection layers comprising openings above the source and drain contact regions, further comprising: a first insulation layer opened over the source and drain contact regions; a second level of said connection layers, establishing a contact with all the source regions and drain regions and a connection between each source (or drain) region and the adjacent source (or drain) regions, with apertures insulating each drain (or source) contact; a second insulation layer opened over the drain (or source) region; and a third continuous level of said connection layers, establishing a contact with all the drain (or source) regions of the second level of said connection layers.

Claim 3

A MOS power transistor structure according to claim 1, wherein: the first level of said connection layers comprises polysilicon and a silicide, and the second and third levels of said connection layers comprise metallizations.

Claim 4

A complementary MOS (CMOS) power transistor structure according to claim 6, further comprising: in a monolithic integrated circuit, an N-DMOS type lateral N-channel transistor and an extended drain type P-MOS lateral P-channel transistor, wherein, in said N-DMOS the channel region thereof is separated from the drain region thereof by a field oxide layer and in the P-MOS said drain extension is formed under a field oxide region.

Claim 5

A complementary MOS (CMOS) transistor structure according to claim 4, wherein: doping of said drain extension region of said P-MOS is provided by an implementation carried out in a self-aligned way before growing of said field oxide, layer thereof.

Claim 6

A complementary MOS (CMOS) power transistor structure in a monolithic integrated circuit, comprising a plurality of MOS power transistors of a first type and a second type, each of said power transistors of either type comprising a plurality of transistor cells each of which comprises on a common face of a substrate gate, source and drain contact zones and three levels of connection layers, a first level of said connection layers establishing a contact with all the gates and a connection between each gate and the adjacent gates, this first level of said connection layers comprising openings above the source and drain contact regions, further comprising: a first insulation layer opened over the source and drain contact regions; a second level of said connection layers, provided such that in a power transistor of said first type said second connection layer is associated with said sources of said transistor cells thereof to provide a connection between each source region and other source regions adjacent thereto, and a MOS power transistor of said second type said second connection layer thereof is associated with said drains thereof to provide a connection between each drain region and adjacent drain regions, said second level of said connection layers each being formed with apertures insulating each respective drain or source contact; a second insulation layer opened over said drain (or source) regions; and a third level of said continuous connection layers for establishing a contact with all of said drain (or source) regions of said second level of said second level of connection layers.

Claim 7

A complementary MOS (CMOS) power transistor structure in a monolithic integrated circuit, comprising a plurality of MOS power transistors of a first type and a second type, each of said power transistors of either type comprising a plurality of transistor cells each of which comprises on a common face of a substrate gate, source and drain contact zones and three levels of connection layers, a first level of said connection layers establishing a contact with all the gates and a connection between each gate and the adjacent gates, this first level of said connection layers comprising openings above the source and drain contact regions, further comprising: a first insulation layer opened over the source and drain contact regions; a second level of said connection layers, provided such that in a power transistor of said first type said second connection layer is associated with said sources of said transistor cells thereof to provide a connection between each source region and other source regions adjacent thereto, and a MOS power transistor of said second type said second connection layer thereof is associated with said drains thereof to provide a connection between each drain region and adjacent drain regions, said second level of said connection layers each being formed with apertures insulating each respective drain or source contact; a second insulation layer opened over said drain (or source) regions; and a third level of said continuous connection layers for establishing a contact with all of said drain (or source) regions of said second level of said second level of connection layers.