General purpose memory access scheme using register-indirect mode

Claim 2

A computer system comprising: (1) first registers for storing data; (2) a second register for storing memory addresses, said second register being architecturally visible such that said second register must be explicitly specified in user-associated instructions to cause memory addresses to be stored in said second register during memory address generation operations; (3) arithmetic-logic means coupled to said first registers for generating said memory addresses from said data during said memory address generation operations; and (4) means coupled to said arithmetic-logic means for writing back said memory addresses to said first registers during said memory address generation operations, and for storing said memory addresses in said second register during said memory address generation operations when said second register is explicitly specified in said user-associated instructions.

Claim 3

The computer system of claim 1, further comprising: (5) a memory coupled to said second register; (6) means for retrieving said memory addresses from said second register during memory access operations; and (7) means for accessing said memory by using said retrieved memory addresses during said memory access operations.

Claim 4

The computer system of claim 2, wherein said first registers and arithmetic-logic means are located on a first circuit board and said second register and memory are located on a second circuit board.

Claim 5

The computer system of claim 1, further comprising: (5) means for saving machine states by transferring said memory addresses in said second register to said first registers.

Claim 6

The computer system of claim 1, wherein an output of said first register is coupled to an input of said arithmetic-logic means.

Claim 7

A computer-based method for accessing a memory, said method for use in a computer system comprising first registers and a second register, the second register being architecturally visible such that the second register must be explicitly specified in user-associated instructions to cause memory addresses to be stored in said second register, said method comprising the steps of: (a) generating a memory address during a memory address generation operation; (b) writing back said memory address to the first registers during said memory address generation operation, and storing said memory address in said second register during said memory address generation operation when the second register is explicitly specified in a user-associated instruction associated with said memory address generation operation; (c) retrieving said memory address from said second register during a memory access operation; and (d) accessing the memory using said retrieved memory address during said memory access operation.

Claim 8

A computer-based method for accessing a memory, said method for use in a computer system comprising first registers and a second register, the second register being architecturally visible such that the second register must be explicitly specified in user-associated instructions to cause memory addresses to be stored in said second register, said method comprising the steps of: (a) generating a memory address during a memory address generation operation; (b) writing back said memory address to the first registers during said memory address generation operation, and storing said memory address in said second register during said memory address generation operation when the second register is explicitly specified in a user-associated instruction associated with said memory address generation operation; (c) retrieving said memory address from said second register during a memory access operation; and (d) accessing the memory using said retrieved memory address during said memory access operation.

Claim 9

The method of claim 6, further comprising the step of saving machine states by transferring said memory addresses in said second register to said first registers.

Claim 10

The method of claim 6, wherein said first registers are located on a first circuit board and said second register and memory are located on a second circuit board.

Claim 11

A computer system comprising: (1) first registers for storing data and memory addresses; (2) a second register for storing said memory addresses; (3) arithmetic-logic means coupled to said first registers for generating said memory addresses from said data during memory address generation operations; (4) means coupled to said arithmetic-logic means for writing back said memory addresses to said first registers and storing said memory addresses in said second register during said memory address generation operations; (5) control means for validating said second register during memory access operations, wherein said second register is valid when said second register contains a valid memory address to access a memory during a memory access operation; and (6) a multiplexer coupled to said first registers, second registers, and arithmetic-logic means for transferring said memory addresses from said first registers to said second register during said memory access operations if said second register is invalid, wherein said second register is invalid when said second register does not contain a valid memory address to access a memory during a memory access operation.

Claim 12

A computer system comprising: (1) first registers for storing data and memory addresses; (2) a second register for storing said memory addresses; (3) arithmetic-logic means coupled to said first registers for generating said memory addresses from said data during memory address generation operations; (4) means coupled to said arithmetic-logic means for writing back said memory addresses to said first registers and storing said memory addresses in said second register during said memory address generation operations; (5) control means for validating said second register during memory access operations, wherein said second register is valid when said second register contains a valid memory address to access a memory during a memory access operation; and (6) a multiplexer coupled to said first registers, second registers, and arithmetic-logic means for transferring said memory addresses from said first registers to said second register during said memory access operations if said second register is invalid, wherein said second register is invalid when said second register does not contain a valid memory address to access a memory during a memory access operation.

Claim 13

The computer system of claim 9, further comprising: (6) a memory coupled to said second register for storing said data; (7) means for retrieving said memory addresses from said second register during said memory access operations; and (8) means for accessing said memory by using said retrieved memory addresses during said memory access operations.

Claim 14

The computer system of claim 10, wherein said means for accessing said memory by using said retrieved memory addresses during said memory access operations comprises means for retrieving said data from said memory.

Claim 15

The computer system of claim 11, further comprising means for writing back said retrieved data to said first registers during said memory access operations if said second register is valid.

Claim 16

The computer system of claim 10, wherein said first registers and arithmetic-logic means are located on a first circuit board and said second register and memory are located on a second circuit board.

Claim 17

The computer system of claim 9, wherein said control means comprises means for determining if said second register contains a valid memory address to access a memory during said memory access operation.

Claim 18

The computer system of claim 14, wherein said means for determining comprises: first means for determining a source register identification of a current memory access operation; second means for determining a destination register identification of an immediately preceding memory address generation operation; and means for comparing said source register identification and destination register identification to determine if said second register is valid, wherein said second register is valid if said source register identification and destination register identification are equal.

Claim 19

The computer system of claim 15, wherein said first registers comprise said source register and destination register.

Claim 20

The computer system of claim 9, wherein an output of said first register is coupled to an input of said arithmetic-logic means.

Claim 21

A computer-based method for accessing a memory, wherein the memory contains data, the method comprising the steps of: (a) generating a memory address during a memory address generation operation; (b) writing back said memory address to first registers and storing said memory address in a second register during said memory address generation operation; and (c) validating said second register during a memory access operation, wherein said second register is valid when said second register contains a valid memory address to access the memory during said memory access operation; (d) retrieving said memory address from said second register during said memory access operation when said second register is valid; and (e) accessing the memory by using said retrieved memory address during said memory access operation; step (c) comprising the steps of: (i) determining a source register identification of a current memory access operation, (ii) determining a destination register identification of an immediately preceding memory address generation operation, (iii) comparing said source register identification and destination register identification to determine if said second register is valid, and (iv) transferring a valid memory address contained in said first registers to said second register if said second register is invalid.

Claim 22

A computer-based method for accessing a memory, wherein the memory contains data, the method comprising the steps of: (a) generating a memory address during a memory address generation operation; (b) writing back said memory address to first registers and storing said memory address in a second register during said memory address generation operation; and (c) validating said second register during a memory access operation, wherein said second register is valid when said second register contains a valid memory address to access the memory during said memory access operation; (d) retrieving said memory address from said second register during said memory access operation when said second register is valid; and (e) accessing the memory by using said retrieved memory address during said memory access operation; step (c) comprising the steps of: (i) determining a source register identification of a current memory access operation, (ii) determining a destination register identification of an immediately preceding memory address generation operation, (iii) comparing said source register identification and destination register identification to determine if said second register is valid, and (iv) transferring a valid memory address contained in said first registers to said second register if said second register is invalid.

Claim 23

The method of claim 18, wherein step (e) comprises the step of retrieving the data from the memory.

Claim 24

The method of claim 19, further comprising the step of writing back said retrieved data to said first registers during said memory access operation if said second register is valid.

Claim 25

The method of claim 18, wherein said first registers comprise said source register and destination register.

Claim 26

The method of claim 18, wherein said first registers are located on a first circuit board and said second register and memory are located on a second circuit board.

Claim 27

The method of claim 18, wherein said first registers and second register are architecturally distinct.

Claim 28

A computer system comprising: (1) first registers for storing data and memory addresses; (2) a second register for storing said memory addresses; (3) a memory coupled to said second register for storing data; (4) arithmetic-logic means coupled to said first registers for generating said memory addresses from said data during memory address generation operations; (5) means coupled to said arithmetic-logic means for writing back said memory addresses to said first registers and storing said memory addresses in said second register during said memory address generation operations; (6) control means for validating said second register during memory access operations, said control means comprising means for determining if said second register contains valid memory addresses to access said memory during said memory access operations, said means for determining comprising: (a) means for determining a source register identification of a current memory access operation; (b) means for determining a destination register identification of an immediately preceding memory address generation operation; and (c) means for comparing said source register identification and destination register identification to determine if said second register is valid, wherein said second register is valid if said source register identification and destination register identification are equal; (7) a multiplexer coupled to said first registers, second register, and arithmetic-logic means for transferring said memory addresses from said first registers to said second register during said memory access operations if said second register is invalid; (8) means for retrieving said memory addresses from said second register during said memory access operations; and (9) means for accessing said memory by using said retrieved memory addresses during said memory access operations.

Claim 29

A computer system comprising: (1) first registers for storing data and memory addresses; (2) a second register for storing said memory addresses; (3) a memory coupled to said second register for storing data; (4) arithmetic-logic means coupled to said first registers for generating said memory addresses from said data during memory address generation operations; (5) means coupled to said arithmetic-logic means for writing back said memory addresses to said first registers and storing said memory addresses in said second register during said memory address generation operations; (6) control means for validating said second register during memory access operations, said control means comprising means for determining if said second register contains valid memory addresses to access said memory during said memory access operations, said means for determining comprising: (a) means for determining a source register identification of a current memory access operation; (b) means for determining a destination register identification of an immediately preceding memory address generation operation; and (c) means for comparing said source register identification and destination register identification to determine if said second register is valid, wherein said second register is valid if said source register identification and destination register identification are equal; (7) a multiplexer coupled to said first registers, second register, and arithmetic-logic means for transferring said memory addresses from said first registers to said second register during said memory access operations if said second register is invalid; (8) means for retrieving said memory addresses from said second register during said memory access operations; and (9) means for accessing said memory by using said retrieved memory addresses during said memory access operations.

Claim 30

The computer system of claim 24, wherein said means for accessing said memory by using said retrieved memory addresses during said memory access operations comprises means for retrieving said data from said memory.

Claim 31

The computer system of claim 25, further comprising means for writing back said retrieved data to said first registers if said second register is valid.

Claim 32

The computer system of claim 24, wherein said first registers and arithmetic-logic means are located on a first circuit board and said second register and memory are located on a second circuit board.

Claim 33

The computer system of claim 24, wherein said first registers comprise said source register and destination register.

Claim 34

The computer system of claim 24, wherein an output of said first register is coupled to an input of said arithmetic-logic means.

Claim 35

A computer-based method for accessing a memory, wherein the memory contains data, the method comprising the steps of: (a) generating a memory address during a memory address generation operation; (b) writing back said memory address to first registers and storing said memory address in a second register during said memory address generation operation; (c) validating said second register during a memory access operation, said step for validating comprising the step of determining if said second register contains a valid memory address to access the memory during said memory access operation, said step of determining comprising the steps of: (1) determining a source register identification of a current memory access operation; (2) determining a destination register identification of an immediately preceding memory address generation operation; (3) comparing said source register identification and destination register identification to determine if said second register is valid, wherein said second register is valid if said source register identification and destination register identification are equal; and (4) transferring a valid memory address contained in said first registers to said second register if said second register is invalid; (d) retrieving said memory address from said second register during said memory access operation; and (e) accessing the memory by using said retrieved memory address during said memory access operation.

Claim 36

A computer-based method for accessing a memory, wherein the memory contains data, the method comprising the steps of: (a) generating a memory address during a memory address generation operation; (b) writing back said memory address to first registers and storing said memory address in a second register during said memory address generation operation; (c) validating said second register during a memory access operation, said step for validating comprising the step of determining if said second register contains a valid memory address to access the memory during said memory access operation, said step of determining comprising the steps of: (1) determining a source register identification of a current memory access operation; (2) determining a destination register identification of an immediately preceding memory address generation operation; (3) comparing said source register identification and destination register identification to determine if said second register is valid, wherein said second register is valid if said source register identification and destination register identification are equal; and (4) transferring a valid memory address contained in said first registers to said second register if said second register is invalid; (d) retrieving said memory address from said second register during said memory access operation; and (e) accessing the memory by using said retrieved memory address during said memory access operation.

Claim 37

The method of claim 30, wherein step (e) comprises the step of retrieving the data from the memory.

Claim 38

The method of claim 31, further comprising the step of writing back said retrieved data to said first registers during said memory access operation if said second register is valid.

Claim 39

The method of claim 30, wherein said first registers comprise said source register and destination register.

Claim 40

The method of claim 30, wherein said first registers are located on a first circuit board and said second register and memory are located on a second circuit board.

Claim 41

The method of claim 30, wherein said first registers and second register are architecturally distinct.