Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
200 words
In a processor having a plurality of memory cells, an integer execution unit, and a bus control unit for processing instructions, including data transfer instructions, in a parallel instruction pipeline, said pipeline including Fetch, Decode, Execute, and Writeback stages, the integer execution unit comprising: a register file comprising at least one write port for writing data and at least one read port for reading data, said register file further having a plurality of registers; a bypass control unit, connected to said read and write ports, for delaying writing of a result of a data transfer instruction into the register file through said write port until the writeback stage of a next data transfer instruction; a shifter, connected to said control bypass unit, for performing logical and arithmetic shift operations; an arithmetic logic unit ("ALU"), connected to said shifter, for calculating effective addresses for said instructions; an internal bus over which data is communicated; an instruction pointer unit, connected to the internal bus, for pointing to the effective address of a next instruction; an instruction control logic unit, connected to said control bypass unit over said internal bus, for storing the next instruction to be executed by said integer execution unit.
Claim 2
Dependent Claim
200 words
In a processor having a plurality of memory cells, an integer execution unit, and a bus control unit for processing instructions, including data transfer instructions, in a parallel instruction pipeline, said pipeline including Fetch, Decode, Execute, and Writeback stages, the integer execution unit comprising: a register file comprising at least one write port for writing data and at least one read port for reading data, said register file further having a plurality of registers; a bypass control unit, connected to said read and write ports, for delaying writing of a result of a data transfer instruction into the register file through said write port until the writeback stage of a next data transfer instruction; a shifter, connected to said control bypass unit, for performing logical and arithmetic shift operations; an arithmetic logic unit ("ALU"), connected to said shifter, for calculating effective addresses for said instructions; an internal bus over which data is communicated; an instruction pointer unit, connected to the internal bus, for pointing to the effective address of a next instruction; an instruction control logic unit, connected to said control bypass unit over said internal bus, for storing the next instruction to be executed by said integer execution unit.
Claim 3
Dependent Claim
24 words
The integer execution unit defined by claim 1, said register file having a plurality of registers, said register file comprising at least 32 registers.
Claim 4
Dependent Claim
28 words
The integer execution unit defined by claim 2, said register file having at least two read ports and one fewer write port than the number of read ports.
Claim 5
Dependent Claim
48 words
The integer execution unit defined by claim 1, said bypass control unit further comprising a plurality of multiplexers coupled to a plurality of latches for holding data, a temporary input register connected to a first one of said multiplexers, and an output register connected to said first multiplexer.
Claim 6
Dependent Claim
35 words
The bypass control unit as defined by claim 4 being coupled to the said ALU and further to said register file for delaying said writeback stage without an extra write port of said register file.
Claim 7
Dependent Claim
77 words
The integer execution unit defined by claim 4, wherein said bypass control unit further comprises means for producing a first signal if a destination address of the result of said data transfer instruction is referenced as a source operand address of a next arithmetic/logic instruction, storing the result in said temporary input register in response to said first signal, and providing the result from said temporary input register to said ALU in response to said first signal.
Claim 8
Dependent Claim
78 words
The integer execution unit defined by claim 4, wherein said bypass control unit further comprises means for producing a second signal if a destination address of the result of said data transfer instruction is referenced as a source operand address of a next store instruction, storing the result in said temporary input register in response to said second signal, and providing the result from said temporary input register to said output register in response to said second signal.