US5367210A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Output buffer with reduced noise
Assignee: Individual
•
Filing: 1992-02-12
•
Granted: 1994-11-22
•
Expires: 2012-02-12
Abstract
Abstract An output buffer and a method provide controlled low noise operation using a current mirror which provides a rapid increase in the gate voltage of an output transistor prior to the gate voltage reaching the threshold voltage of the output transistor and provide a constant current voltage ramp thereafter. In one embodiment, the present invention automatically compensates for normal variations in transistor channel length due to fluctuations of process parameters. In one embodiment, a mechanism for switching off the current mirror is provided to reduce power consumption.
Inventors
- 👤 Robert J. Lipp
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 18:35
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0008; H03K19/0013; H03K17/00; H03K17/16; H03K17/161; H03K17/162; H03K17/163; H03K19/003; H03K19/00346; H03K19/00361; H03K2217/00; H03K2217/0036
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
152 words
An output buffer comprising: a driver stage including an output transistor having a gate terminal for receiving a voltage, said output transistor having low impedance and high impedance states determined by whether said voltage is higher or lower than a threshold voltage, said driver stage providing a feedback signal to indicate whether said voltage is higher or lower than said threshold voltage; and means for controlling said driver stage, receiving said feedback signal, said means for controlling causing said output transistor to transition from said high impedance state to said low impedance state by providing at said gate terminal of said output transistor, prior to said voltage reaching said threshold voltage, as indicated by said feedback signal, a varying rate of voltage increase, and providing, after said threshold voltage is reached, as indicated by said feedback signal, a substantially constant rate of voltage increase less than said varying rate of voltage increase.
Claim 2
Dependent Claim
152 words
An output buffer comprising: a driver stage including an output transistor having a gate terminal for receiving a voltage, said output transistor having low impedance and high impedance states determined by whether said voltage is higher or lower than a threshold voltage, said driver stage providing a feedback signal to indicate whether said voltage is higher or lower than said threshold voltage; and means for controlling said driver stage, receiving said feedback signal, said means for controlling causing said output transistor to transition from said high impedance state to said low impedance state by providing at said gate terminal of said output transistor, prior to said voltage reaching said threshold voltage, as indicated by said feedback signal, a varying rate of voltage increase, and providing, after said threshold voltage is reached, as indicated by said feedback signal, a substantially constant rate of voltage increase less than said varying rate of voltage increase.
Claim 3
Dependent Claim
94 words
An output buffer as in claim 1, wherein said means for controlling comprises: means for rapidly bringing an electrical node to a reference voltage; means, coupled to said electrical node and said gate terminal, for providing a varying current prior to said electrical node is brought to said reference voltage and for providing a substantially constant current after said electrical node is brought to said reference voltage, said varying current and said substantially constant current causing said varying rate of voltage increase and said substantially constant rate of voltage increase at said gate terminal.
Claim 4
Dependent Claim
265 words
An output buffer comprising: a driver stage including an output transistor having a gate terminal for receiving a voltage, said output transistor having low impedance and high impedance states determined by whether said voltage is higher or lower than a threshold voltage, said driver state providing a feedback signal to indicate whether said voltage is higher or lower than said threshold voltage; and means for controlling said driver stage, receiving said feedback signal, said means for controlling causing said output transistor to transition from said high impedance state by providing at said gate terminal of said output transistor, prior to said voltage reaching said threshold voltage, as indicated by said feedback signal, a varying rate of voltage increase, and providing, after said threshold voltage is reached, as indicated by said feedback signal, a substantially constant rate of voltage increase less than said varying rate of voltage increase, wherein said means for controlling comprises: means for rapidly bringing an electrical node to a reference voltage, means, coupled to said electrical node and said gate terminal, for providing a varying current prior to said electrical node is brought to said reference voltage and for providing a substantially constant current after said electrical node is brought to said reference voltage, said varying current and said substantially constant current causing said varying and substantially constant voltage at said gate terminal, wherein said means for providing a varying current comprises a current mirror, and wherein said means for rapidly bringing an electrical node to a reference voltage comprises a transistor connected between a reference voltage source and said current mirror.
Claim 5
Dependent Claim
265 words
An output buffer comprising: a driver stage including an output transistor having a gate terminal for receiving a voltage, said output transistor having low impedance and high impedance states determined by whether said voltage is higher or lower than a threshold voltage, said driver state providing a feedback signal to indicate whether said voltage is higher or lower than said threshold voltage; and means for controlling said driver stage, receiving said feedback signal, said means for controlling causing said output transistor to transition from said high impedance state by providing at said gate terminal of said output transistor, prior to said voltage reaching said threshold voltage, as indicated by said feedback signal, a varying rate of voltage increase, and providing, after said threshold voltage is reached, as indicated by said feedback signal, a substantially constant rate of voltage increase less than said varying rate of voltage increase, wherein said means for controlling comprises: means for rapidly bringing an electrical node to a reference voltage, means, coupled to said electrical node and said gate terminal, for providing a varying current prior to said electrical node is brought to said reference voltage and for providing a substantially constant current after said electrical node is brought to said reference voltage, said varying current and said substantially constant current causing said varying and substantially constant voltage at said gate terminal, wherein said means for providing a varying current comprises a current mirror, and wherein said means for rapidly bringing an electrical node to a reference voltage comprises a transistor connected between a reference voltage source and said current mirror.
Claim 6
Dependent Claim
30 words
An output buffer as in claim 3, further comprising means for disabling said means for providing a varying current in response to said output transistor reaching said low impedance state.
Claim 7
Independent Claim
130 words
A method for providing a low noise output buffer, comprising the steps of: receiving a voltage on a gate terminal of an output transistor, said output transistor being part of a driver stage of said low noise output buffer, said output transistor having low impedance and high impedance states determined by whether said voltage is higher or lower than a threshold voltage, providing a feedback signal indicating whether said voltage is higher or lower than said threshold voltage; and controlling said driver stage to cause said output transistor to transition from said low impedance state to said high impedance state by increasing said voltage at a varying rate until said voltage reaches said threshold voltage, as indicated by said feedback signal, then increasing said voltage at a substantially constant rate.
Claim 8
Independent Claim
130 words
A method for providing a low noise output buffer, comprising the steps of: receiving a voltage on a gate terminal of an output transistor, said output transistor being part of a driver stage of said low noise output buffer, said output transistor having low impedance and high impedance states determined by whether said voltage is higher or lower than a threshold voltage, providing a feedback signal indicating whether said voltage is higher or lower than said threshold voltage; and controlling said driver stage to cause said output transistor to transition from said low impedance state to said high impedance state by increasing said voltage at a varying rate until said voltage reaches said threshold voltage, as indicated by said feedback signal, then increasing said voltage at a substantially constant rate.
Claim 9
Dependent Claim
86 words
A method as in claim 5, wherein said step of controlling comprises: rapidly bringing an electrical node to a reference voltage; supplying a varying current at said electrical node until said reference voltage is reached, said varying current bringing charge to said gate terminal thereby increasing said voltage at said varying rate; and supplying a substantially constant current at said electrical node after said reference voltage is reached, said varying current bringing charge to said gate terminal thereby increasing said voltage at said substantially constant rate.
Claim 10
Independent Claim
259 words
A method for providing a low noise output buffer, comprising the steps of: receiving a voltage on a gate terminal of an output transistor, said output transistor being part of a driver stage of said low noise output buffer, said output transistor having a low impedance and high impedance states determined by whether said voltage is higher or lower than a threshold voltage; providing a feedback signal indicating whether said voltage is higher or lower than said threshold voltage; and controlling said driver stage to cause said output transistor to transition from said low impedance state to said high impedance state by increasing said voltage at a varying rate until said voltage reaches said threshold voltage, as indicated by said feedback signal, then increasing said voltage at a substantially constant rate, wherein said step of controlling further comprises the steps of: rapidly bringing an electrical node to a reference voltage; and supplying a varying current at said electrical node until said reference voltage is reached, then supplying a substantially constant current at said electrical node, said varying current and said substantially constant current bringing charge to said gate terminal to cause said varying and substantially constant increases in said voltage at said gate terminal, wherein said step of supplying a varying current comprises the step of using a current mirror to supply said varying current and said substantially constant current and wherein said step of rapidly bringing an electrical node to a reference voltage comprises switching on a transistor coupled between a reference voltage source and said current mirror.
Claim 11
Independent Claim
259 words
A method for providing a low noise output buffer, comprising the steps of: receiving a voltage on a gate terminal of an output transistor, said output transistor being part of a driver stage of said low noise output buffer, said output transistor having a low impedance and high impedance states determined by whether said voltage is higher or lower than a threshold voltage; providing a feedback signal indicating whether said voltage is higher or lower than said threshold voltage; and controlling said driver stage to cause said output transistor to transition from said low impedance state to said high impedance state by increasing said voltage at a varying rate until said voltage reaches said threshold voltage, as indicated by said feedback signal, then increasing said voltage at a substantially constant rate, wherein said step of controlling further comprises the steps of: rapidly bringing an electrical node to a reference voltage; and supplying a varying current at said electrical node until said reference voltage is reached, then supplying a substantially constant current at said electrical node, said varying current and said substantially constant current bringing charge to said gate terminal to cause said varying and substantially constant increases in said voltage at said gate terminal, wherein said step of supplying a varying current comprises the step of using a current mirror to supply said varying current and said substantially constant current and wherein said step of rapidly bringing an electrical node to a reference voltage comprises switching on a transistor coupled between a reference voltage source and said current mirror.
Claim 12
Dependent Claim
27 words
A method as in claim 6 further comprising the step of disabling said substantially constant current in response to said output transistor reaching said low impedance state.
Claim 13
Dependent Claim
187 words
A current mirror comprising: a first MOS transistor having gate, source and drain terminals, said source terminal coupled to a first reference voltage source said gate terminal coupled to said drain terminal; a second MOS transistor coupled between said drain terminal of said first MOS transistor and a second reference terminal; and a third MOS transistor having gate, source and drain terminals, said gate terminal of said third MOS transistor coupled to said gate terminal of said first MOS transistor, said source terminal of said third MOS transistor coupled to said first reference voltage source and said drain terminal of said third MOS transistor coupled to a current receiving load; wherein said second and third MOS transistors each have a channel length longer than the channel length of said first MOS transistor, such that a variation in channel length in the course of manufacturing said first, second and third MOS transistors reducing the current flowing in said second transistor causes a corresponding gain in said current mirror to provide a net gain in a current flowing between said source and drain terminals of said second MOS transistor.
Claim 14
Dependent Claim
187 words
A current mirror comprising: a first MOS transistor having gate, source and drain terminals, said source terminal coupled to a first reference voltage source said gate terminal coupled to said drain terminal; a second MOS transistor coupled between said drain terminal of said first MOS transistor and a second reference terminal; and a third MOS transistor having gate, source and drain terminals, said gate terminal of said third MOS transistor coupled to said gate terminal of said first MOS transistor, said source terminal of said third MOS transistor coupled to said first reference voltage source and said drain terminal of said third MOS transistor coupled to a current receiving load; wherein said second and third MOS transistors each have a channel length longer than the channel length of said first MOS transistor, such that a variation in channel length in the course of manufacturing said first, second and third MOS transistors reducing the current flowing in said second transistor causes a corresponding gain in said current mirror to provide a net gain in a current flowing between said source and drain terminals of said second MOS transistor.
Claim 15
Dependent Claim
195 words
An output buffer as in claim 3, wherein said current mirror comprises: a first MOS transistor having gate, source and drain terminals, said source terminal coupled to said reference voltage source said gate terminal coupled to said drain terminal; a second MOS transistor coupled between said drain terminal of said first MOS transistor and a second reference terminal; and a third MOS transistor having gate, source and drain terminals, said gate terminal of said third MOS transistor coupled to said gate terminal of said first MOS transistor, said source terminal of said third MOS transistor coupled to said reference voltage source and said drain terminal of third MOS transistor coupled to said gate terminal of said output transistor; wherein said second and third MOS transistors each have a channel length longer than the channel length of said first MOS transistor, such that a variation in channel length in the course of manufacturing said first, second and third MOS transistors reducing the current flowing in said second transistor causes a corresponding gain in said current mirror to provide a net gain in a current flowing between said source and drain terminals of said second MOS transistor.
Claim 16
Independent Claim
422 words
A method for providing a low noise output buffer, comprising the steps of: receiving a voltage on a gate terminal of an output transistor, said output transistor being part of a driver stage of said low noise output buffer, said output transistor having low impedance and high impedance states determined by whether said voltage is higher or lower than a threshold voltage; providing a feedback signal indicating whether said voltage is higher or lower than said threshold voltage; and controlling said driver stage to cause said output transistor to transition from said low impedance state to said high impedance state by increasing said voltage at a varying rate until said voltage reaches said threshold voltage, as indicated by said feedback signal, then increasing said voltage at a substantially constant rate, wherein said step of controlling further comprises the steps of: rapidly bringing an electrical node to a reference voltage; and supplying a varying current at said electrical node until said reference voltage is reached, then supplying a substantially constant current at said electrical node, said varying current and said substantially constant current bringing charge to said gate terminal to cause said varying and substantially constant increases in said voltage at said gate terminal, wherein said step of supplying a varying current and substantially constant current comprises the steps of: coupling a first MOS transistor having gate, source and drain terminals to a first reference source, said source terminal of said first MOS transistor coupled to said first reference voltage sources; coupling a second MOS transistor between said drain terminal of said first MOS transistor and a second reference terminal; and coupling a third MOS transistor having gate, source and drain terminals to said first MOS transistor, said first reference voltage source, and a current receiving node, said gate terminal of said third MOS transistor coupled to said gate terminal of said first MOS transistor, said source terminal of said third MOS transistor coupled to said first reference voltage source, and said drain terminal of said third MOS transistor coupled to said current receiving node; wherein each of said second and third MOS transistors has a channel length longer than the channel length of said first MOS transistor, such that a variation of channel length in the course of manufacturing said first, second and third MOS transistors reducing the current flowing in said second transistor causes a corresponding gain in said current mirror to provide a net gain in a current flowing between said source and drain terminals of said second MOS transistor.
Claim 17
Independent Claim
422 words
A method for providing a low noise output buffer, comprising the steps of: receiving a voltage on a gate terminal of an output transistor, said output transistor being part of a driver stage of said low noise output buffer, said output transistor having low impedance and high impedance states determined by whether said voltage is higher or lower than a threshold voltage; providing a feedback signal indicating whether said voltage is higher or lower than said threshold voltage; and controlling said driver stage to cause said output transistor to transition from said low impedance state to said high impedance state by increasing said voltage at a varying rate until said voltage reaches said threshold voltage, as indicated by said feedback signal, then increasing said voltage at a substantially constant rate, wherein said step of controlling further comprises the steps of: rapidly bringing an electrical node to a reference voltage; and supplying a varying current at said electrical node until said reference voltage is reached, then supplying a substantially constant current at said electrical node, said varying current and said substantially constant current bringing charge to said gate terminal to cause said varying and substantially constant increases in said voltage at said gate terminal, wherein said step of supplying a varying current and substantially constant current comprises the steps of: coupling a first MOS transistor having gate, source and drain terminals to a first reference source, said source terminal of said first MOS transistor coupled to said first reference voltage sources; coupling a second MOS transistor between said drain terminal of said first MOS transistor and a second reference terminal; and coupling a third MOS transistor having gate, source and drain terminals to said first MOS transistor, said first reference voltage source, and a current receiving node, said gate terminal of said third MOS transistor coupled to said gate terminal of said first MOS transistor, said source terminal of said third MOS transistor coupled to said first reference voltage source, and said drain terminal of said third MOS transistor coupled to said current receiving node; wherein each of said second and third MOS transistors has a channel length longer than the channel length of said first MOS transistor, such that a variation of channel length in the course of manufacturing said first, second and third MOS transistors reducing the current flowing in said second transistor causes a corresponding gain in said current mirror to provide a net gain in a current flowing between said source and drain terminals of said second MOS transistor.
Claim 18
Dependent Claim
186 words
An output buffer having an input and output terminal, comprising: a driver stage receiving a first signal at a first terminal and providing a second signal complementary to said first signal on said output terminal; and a predriver stage coupled to said input terminal, comprising: a first MOS transistor having a gate terminal coupled to said input terminal, a source terminal coupled to a first reference voltage source, and a drain terminal; a second MOS transistor having a source terminal coupled to said drain terminal of said first MOS transistor, a drain terminal coupled to said first terminal of said driver stage, and a gate terminal; a current mirror control circuit coupled to the gate terminal of said second MOS transistor for regulating a current flowing between said source and drain terminals of said second MOS transistor; and a third MOS transistor having a drain terminal coupled to said first terminal of said driver stage, a gate terminal coupled to said input terminal and a source terminal coupled to a second reference voltage source; wherein said current mirror is enabled and disabled by said second signal.
Claim 19
Dependent Claim
186 words
An output buffer having an input and output terminal, comprising: a driver stage receiving a first signal at a first terminal and providing a second signal complementary to said first signal on said output terminal; and a predriver stage coupled to said input terminal, comprising: a first MOS transistor having a gate terminal coupled to said input terminal, a source terminal coupled to a first reference voltage source, and a drain terminal; a second MOS transistor having a source terminal coupled to said drain terminal of said first MOS transistor, a drain terminal coupled to said first terminal of said driver stage, and a gate terminal; a current mirror control circuit coupled to the gate terminal of said second MOS transistor for regulating a current flowing between said source and drain terminals of said second MOS transistor; and a third MOS transistor having a drain terminal coupled to said first terminal of said driver stage, a gate terminal coupled to said input terminal and a source terminal coupled to a second reference voltage source; wherein said current mirror is enabled and disabled by said second signal.
Claim 20
Dependent Claim
52 words
An output buffer as in claim 12, wherein said predriver stage further comprises a fourth MOS transistor having a gate terminal coupled to said second signal, a source terminal coupled to said drain terminal of said first MOS transistor, and a drain terminal coupled to said first terminal of said driver stage.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-21 | 1998-05-23 | 1998-11-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-21 | 2002-05-23 | 2002-11-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-21 | 2006-05-23 | 2006-11-22 | $7700.00 | Window Closed / Lapsed |