Integrated semiconductor device having a buried semiconductor layer and fabrication method thereof

Claim 2

An integrated semiconductor device comprising: a semiconductor substrate having a surface and a surface portion bordering the surface, the surface portion having a first conductivity type; an insulating layer formed on said semiconductor substrate, said insulating layer having a plurality of windows, each window exposing a part of a surface of the surface portion; a semiconductor layer formed on the exposed parts of the surface of the surface portion, said semiconductor layer further comprising; a buried semiconductor layer of the first conductivity type having an upper surface in said semiconductor layer; a first region of the first conductivity type formed above the buried semiconductor layer and adjacent to a surface thereof, the first region of the first conductivity type having an impurity concentration lower than an impurity concentration of the buried semiconductor layer; a pair of second regions of a second conductivity type opposite to the first conductivity type formed above the buried semiconductor layer and adjacent to the surface thereof, each one of the pair of second regions separated from the other one of the pair of second regions by the first region of the first conductivity type; and a plurality of active elements formed in said semiconductor layer within selected ones of the windows, each of the active elements further comprising: the first region of the first conductivity type, and the pair of second regions of the second conductivity type.

Claim 3

The integrated semiconductor device of claim 1, wherein each of selected ones of said plurality of active elements comprises: an insulated gate field effect transistor having a channel region and source and drain regions; the channel region comprising the first region of the first conductivity type, and the source and drain regions comprising respective ones of the pair of second regions of the second conductivity type opposite to the first conductivity type.

Claim 4

The integrated semiconductor device of claim 1, wherein each of selected ones of said active elements comprises: an insulated gate film on a top surface of the first region of the first conductivity type; and an insulated gate electrode formed on said insulated gate film across a corresponding one of the windows and extending over a surface of said insulating layer on said semiconductor substrate.

Claim 5

The integrated semiconductor device of claim 1, wherein a top surface of said semiconductor layer of the first conductivity type has substantially the same plane as a top surface of said insulating layer.

Claim 6

The device of claim 1, wherein the buried semiconductor layer has an impurity profile with a peak value of impurity concentration higher than an impurity concentration of the surface portion of said semiconductor substrate.

Claim 7

The integrated semiconductor device of claim 5, wherein the buried semiconductor layer has said impurity profile with said impurity concentration decreasing monotonously from a location of the peak value toward the first region of said semiconductor layer.

Claim 8

The integrated semiconductor device of claim 1, wherein the buried semiconductor layer has an impurity profile with the upper surface which is not deeper than a pn junction depth of each one of the pair of second regions.

Claim 9

The integrated semiconductor device of claim 1, wherein the buried semiconductor layer has a lower surface which is in said semiconductor layer.

Claim 10

The integrated semiconductor device of claim 1, wherein said buried semiconductor layer has a lower surface in the surface portion of said semiconductor substrate.

Claim 11

The integrated semiconductor device of claim 1, wherein a pn junction depth of each one of the pair of second regions is shallower than the surface of said semiconductor substrate.

Claim 12

The integrated semiconductor device of claim 1, wherein said semiconductor substrate of the first conductivity type is replaced by a semiconductor substrate of a second conductivity type opposite to the first conductivity type.

Claim 13

The integrated semiconductor device of claim 1, wherein said device has a groove at a top surface of said semiconductor layer around the window of said insulating layer, the groove filled with an insulating material so that the top surface is planar and smooth.

Claim 14

The integrated semiconductor device of claim 2, wherein a plurality of the channel regions of the first conductivity type are formed in a single surface portion of the semiconductor substrate, and each one of the pairs of source and drain regions are isolated from the other one of the pairs by the insulating layer with a channel stop therebetween.

Claim 15

An integrated semiconductor device comprising: a semiconductor substrate of a first conductivity type having a first well of the first conductivity type and a second well of a second conductivity type opposite to the first conductivity type so that the first well is separated from the second well; an insulating layer on said semiconductor substrate, said insulating layer having a plurality of first and second windows, each of the windows exposing each surface of the first and second wells, respectively; an epitaxial semiconductor layer selectively formed on each of the exposed surfaces of the first and second wells, each of said epitaxial semiconductor layers having the same conductivity as, and lower impurity concentration than an impurity concentration of each of the underlaid wells; a plurality of first insulated gate effect transistors selectively formed within the first windows, each of said insulated gate effect transistors having a first insulated gate electrode formed on an insulated gate film across the first window, a first channel region of the first conductivity type and a first pair of source and drain regions of the second conductivity type opposite to the first conductivity type formed in the epitaxial semiconductor layer, so that the first channel region of the first conductivity type is formed between the pair of source and drain regions and under the first insulated gate electrode; a plurality of second insulated gate effect transistors selectively formed within the second windows, each of the insulated gate effect transistors having a second insulated gate electrode formed on an insulated gate film across the second window, a second channel region of the second conductivity type and a second pair of source and drain regions of the first conductivity type formed in the epitaxial semiconductor layer, so that the second channel region of the second conductivity type is formed between the pair of source and drain regions and under the second insulated gate electrode; a buried semiconductor layer of the first conductivity type selectively formed in said epitaxial semiconductor layer of the first conductivity type, said buried semiconductor layer of the first conductivity type having a higher impurity concentration than an impurity concentration of the first channel region of the first conductivity type; and a buried semiconductor layer of a second conductivity type selectively formed in said epitaxial semiconductor layer of the second conductivity type, said buried semiconductor layer of the second conductivity type having higher impurity concentration than an impurity concentration of the second channel region of the second conductivity type.

Claim 16

An integrated semiconductor device comprising: a semiconductor substrate of a first conductivity type having a first well of the first conductivity type and a second well of a second conductivity type opposite to the first conductivity type so that the first well is separated from the second well; an insulating layer on said semiconductor substrate, said insulating layer having a plurality of first and second windows, each of the windows exposing each surface of the first and second wells, respectively; an epitaxial semiconductor layer selectively formed on each of the exposed surfaces of the first and second wells, each of said epitaxial semiconductor layers having the same conductivity as, and lower impurity concentration than an impurity concentration of each of the underlaid wells; a plurality of first insulated gate effect transistors selectively formed within the first windows, each of said insulated gate effect transistors having a first insulated gate electrode formed on an insulated gate film across the first window, a first channel region of the first conductivity type and a first pair of source and drain regions of the second conductivity type opposite to the first conductivity type formed in the epitaxial semiconductor layer, so that the first channel region of the first conductivity type is formed between the pair of source and drain regions and under the first insulated gate electrode; a plurality of second insulated gate effect transistors selectively formed within the second windows, each of the insulated gate effect transistors having a second insulated gate electrode formed on an insulated gate film across the second window, a second channel region of the second conductivity type and a second pair of source and drain regions of the first conductivity type formed in the epitaxial semiconductor layer, so that the second channel region of the second conductivity type is formed between the pair of source and drain regions and under the second insulated gate electrode; a buried semiconductor layer of the first conductivity type selectively formed in said epitaxial semiconductor layer of the first conductivity type, said buried semiconductor layer of the first conductivity type having a higher impurity concentration than an impurity concentration of the first channel region of the first conductivity type; and a buried semiconductor layer of a second conductivity type selectively formed in said epitaxial semiconductor layer of the second conductivity type, said buried semiconductor layer of the second conductivity type having higher impurity concentration than an impurity concentration of the second channel region of the second conductivity type.

Claim 17

An integrated semiconductor device comprising: a semiconductor substrate having a surface, a first surface portion bordering a part of the surface, and an second surface portion bordering another part of the surface, the first surface portion having a first conductivity type and the second surface portion having a second conductivity type opposite to the first conductivity type; an insulating layer formed on said semiconductor substrate, said insulating layer having a first window exposing a part of the first surface portion and a second window exposing a part of the second surface portion; a first semiconductor layer selectively formed on the first surface portion within the first window of said insulating layer, said first semiconductor layer further comprising; a first buried semiconductor layer of a first conductivity type having an upper surface in said first semiconductor layer, a first region of the first conductivity type adjacent to a surface of said first semiconductor layer and above the first buried semiconductor layer, the first region of the first conductivity type having an impurity concentration lower an than impurity concentration of the first buried semiconductor layer, and a pair of second regions of a second conductivity type opposite to the first conductivity type adjacent to a surface of said first semiconductor layer, each one of the pair of second regions separated from the other one of the pair of second regions by the first region of the first conductivity type, and a second semiconductor layer selectively formed on the second surface portion within the second window of said insulating layer, said second semiconductor layer further comprising; a second buried semiconductor layer of the second conductivity type having an upper surface in said second semiconductor layer, a third region of the second conductivity type adjacent to a surface of said second semiconductor layer and above said second buried semiconductor layer, the third region of the second conductivity type having an impurity concentration lower than an impurity concentration of the second buried semiconductor layer, and a pair of fourth regions of the first conductivity type adjacent to the surface of said second semiconductor layer, each one of the pair of the fourth regions separated from the other one of the pair of the fourth regions by the third region of the second conductivity type; a first insulated gate field effect transistor having a first channel region formed in the first region of the first conductivity type and a first pair of source and drain region formed in the pair of second region in said first semiconductor layer; and a second insulted gate field effect transistor having a second channel region formed in the third region of the second conductivity type and a second pair of source and drain region formed in the pair of fourth regions formed in said second semiconductor layer.

Claim 18

An integrated semiconductor device comprising: a semiconductor substrate having a surface, a first surface portion bordering a part of the surface, and an second surface portion bordering another part of the surface, the first surface portion having a first conductivity type and the second surface portion having a second conductivity type opposite to the first conductivity type; an insulating layer formed on said semiconductor substrate, said insulating layer having a first window exposing a part of the first surface portion and a second window exposing a part of the second surface portion; a first semiconductor layer selectively formed on the first surface portion within the first window of said insulating layer, said first semiconductor layer further comprising; a first buried semiconductor layer of a first conductivity type having an upper surface in said first semiconductor layer, a first region of the first conductivity type adjacent to a surface of said first semiconductor layer and above the first buried semiconductor layer, the first region of the first conductivity type having an impurity concentration lower an than impurity concentration of the first buried semiconductor layer, and a pair of second regions of a second conductivity type opposite to the first conductivity type adjacent to a surface of said first semiconductor layer, each one of the pair of second regions separated from the other one of the pair of second regions by the first region of the first conductivity type, and a second semiconductor layer selectively formed on the second surface portion within the second window of said insulating layer, said second semiconductor layer further comprising; a second buried semiconductor layer of the second conductivity type having an upper surface in said second semiconductor layer, a third region of the second conductivity type adjacent to a surface of said second semiconductor layer and above said second buried semiconductor layer, the third region of the second conductivity type having an impurity concentration lower than an impurity concentration of the second buried semiconductor layer, and a pair of fourth regions of the first conductivity type adjacent to the surface of said second semiconductor layer, each one of the pair of the fourth regions separated from the other one of the pair of the fourth regions by the third region of the second conductivity type; a first insulated gate field effect transistor having a first channel region formed in the first region of the first conductivity type and a first pair of source and drain region formed in the pair of second region in said first semiconductor layer; and a second insulted gate field effect transistor having a second channel region formed in the third region of the second conductivity type and a second pair of source and drain region formed in the pair of fourth regions formed in said second semiconductor layer.