US5362678A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing insulated via hole structure for semiconductor device
Assignee: Mitsubishi Electric Corp
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Filing: 1993-02-12
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Granted: 1994-11-08
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Expires: 2013-02-12
Abstract
Abstract A semiconductor device includes a semiconductor substrate, first and second semiconductor layers of opposite conductivity types successively disposed on the semiconductor substrate, and a via hole structure including a hole penetrating through the first and second semiconductor layers and into the substrate, the via holes being defined by a side wall of the first and second layers and of the substrate, an electrically conducting material disposed on the side wall contacting the first and second semiconductor layers, and an electrically isolating region disposed in the first and second layers at the side wall and contacting the electrically conducting material. The electrically isolating region is formed with an ion flux applied either before or after etching of the via hole.
Inventors
- 👤 Makio Komaru
- 👤 Michihiro Kobiki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 05:10
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/254; Y; Y10; Y10S; Y10S148/00; Y10S148/05
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
138 words
A method of making a semiconductor device comprising: depositing first and second semiconductor layers of opposite conductivity types on a semiconductor substrate; exposing the second semiconductor layer to a flux of ions to produce an electrically isolating region in and penetrating through the first and second semiconductor layers and into the semiconductor substrate; etching a via hole penetrating through the first and second semiconductor layers within the electrically isolating region, thereby exposing a side wall of the first and second semiconductor layers within the electrically isolating region; and depositing an electrically conducting material in the via hole in contact with the side wall of the first and second semiconductor layers at the electrically isolating region, thereby completing a via hole structure in which the first and second semiconductor films are not electrically connected through the electrically conducting material.
Claim 2
Independent Claim
138 words
A method of making a semiconductor device comprising: depositing first and second semiconductor layers of opposite conductivity types on a semiconductor substrate; exposing the second semiconductor layer to a flux of ions to produce an electrically isolating region in and penetrating through the first and second semiconductor layers and into the semiconductor substrate; etching a via hole penetrating through the first and second semiconductor layers within the electrically isolating region, thereby exposing a side wall of the first and second semiconductor layers within the electrically isolating region; and depositing an electrically conducting material in the via hole in contact with the side wall of the first and second semiconductor layers at the electrically isolating region, thereby completing a via hole structure in which the first and second semiconductor films are not electrically connected through the electrically conducting material.
Claim 3
Dependent Claim
40 words
The method of claim 1 including depositing source, gate, and drain electrodes on the second semiconductor layer to form a field effect transistor and depositing the electrically conducting material in electrical contact with one of the source and gate electrodes.
Claim 4
Dependent Claim
27 words
The method of claim 1 wherein the substrate is semi-insulating including depositing a plated heat sink on the surface of the substrate opposite the first semiconductor layer.
Claim 5
Dependent Claim
19 words
The method of claim 3 including depositing the electrically conducting material in electrical contact with the plated heat sink.
Claim 6
Dependent Claim
21 words
The method of claim 1 wherein the semiconductor substrate is chosen from the group consisting of gallium arsenide and indium phosphide.
Claim 7
Dependent Claim
11 words
The method of claim 1 wherein the semiconductor substrate is silicon.
Claim 8
Dependent Claim
24 words
The method of claim 1 including etching the via hole through the substrate, the first semiconductor layer, and finally through the second semiconductor layer.
Claim 9
Dependent Claim
27 words
The method of claim 7 including depositing the electrically conducting material in the via hole and on the surface of the substrate opposite the first semiconductor layer.
Claim 10
Independent Claim
150 words
A method of making a semiconductor device comprising: depositing first and second semiconductor layers of opposite conductivity types on a semiconductor substrate; etching a via hole penetrating through the first and second semiconductor layers and into the semiconductor substrate, thereby exposing a side wall of the first and second semiconductor layers; exposing the surface of the second semiconductor layer to a flux of ions to produce an electrically isolating region in and penetrating through the first and second semiconductor layers and into the semiconductor substrate surrounding the via hole to produce an electrically isolating region adjacent the side wall; and depositing an electrically conducting material in the via hole in contact with the side wall of the first and second semiconductor layers at the electrically isolating region, thereby completing a via hole structure in which the first and second semiconductor films are not electrically connected through the electrically conducting material.
Claim 11
Independent Claim
150 words
A method of making a semiconductor device comprising: depositing first and second semiconductor layers of opposite conductivity types on a semiconductor substrate; etching a via hole penetrating through the first and second semiconductor layers and into the semiconductor substrate, thereby exposing a side wall of the first and second semiconductor layers; exposing the surface of the second semiconductor layer to a flux of ions to produce an electrically isolating region in and penetrating through the first and second semiconductor layers and into the semiconductor substrate surrounding the via hole to produce an electrically isolating region adjacent the side wall; and depositing an electrically conducting material in the via hole in contact with the side wall of the first and second semiconductor layers at the electrically isolating region, thereby completing a via hole structure in which the first and second semiconductor films are not electrically connected through the electrically conducting material.
Claim 12
Dependent Claim
40 words
The method of claim 9 including depositing source, gate, and drain electrodes on the second semiconductor layer to form a field effect transistor and depositing the electrically conducting material in electrical contact with one of the source and gate electrodes.
Claim 13
Dependent Claim
27 words
The method of claim 9 wherein the substrate is semi-insulating including depositing a plated heat sink on the substrate on the surface opposite the first semiconductor layer.
Claim 14
Dependent Claim
19 words
The method of claim 11 including depositing the electrically conducting material in electrical contact with the plated heat sink.
Claim 15
Dependent Claim
21 words
The method of claim 9 wherein the semiconductor substrate is chosen from the group consisting of gallium arsenide and indium phosphide.
Claim 16
Dependent Claim
11 words
The method of claim 9 wherein the semiconductor substrate is silicon.
Claim 17
Dependent Claim
24 words
The method of claim 9 including etching the via hole through the substrate, the first semiconductor layer, and finally through the second semiconductor layer.
Claim 18
Dependent Claim
27 words
The method of claim 15 including depositing the electrically conducting material in the via hole and on the surface of the substrate opposite the first semiconductor layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-07 | 1998-05-09 | 1998-11-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-07 | 2002-05-09 | 2002-11-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-07 | 2006-05-09 | 2006-11-08 | $7700.00 | Window Closed / Lapsed |