EP0376723A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Structure and process for producing a substrate tap in a bipolar structure and process for forming same
Assignee: Microchip Technology Inc
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Filing: 1989-12-28
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Granted: —
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Expires: 2009-12-28
Abstract
Abstract A substrate tap is incorporated in an integrated circuit which comprises a plurality of transistors formed in isolated device regions in a substrate material comprising a layer of N-type material over a layer of P-type material. The isolated device regions are defined by isolating slots extending down through said N-type material and into the P-type material. The trench for each substrate tap extend down to said P-type material and has an oxide layer lining the sidewalls of trench, a doped polysilicon layer covering the sides and bottom of said trench, and a doped implant or diffused region formed at the base of and in contact between the tap and the substrate. The substrate beneath the devices is connected to a negative potential to isolate the devices on said substrate. Preferably, the substrate tap includes a silicide layer formed over said polysilicon layer to enhance contact to said doped implant region.
Inventors
- 👤 Larry Joseph Pollock
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 17:30
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/041; H10W10/40
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
148 words
A substrate tap incorporated in an integrated circuit comprising a plurality of transistors formed in isolated device regions where the transistors will be formed in a substrate material comprising a layer of N-type material over a layer of P-type substrate material, the isolated device regions being defined by isolating slots surrounding said regions and extending down through said N-type material and into said P-type material, the trench for said substrate tap extending down to said P-type material, an oxide layer lining the sidewalls of trench, a doped polysilicon layer covering the sides and bottom of said trench, and a doped implant or diffused region formed at the base of and in contact with the bottom of said substrate tap to establish contact between said tap and said substrate, and means for connecting the substrate beneath said devices to a negative potential to isolate the devices on said substrate.
Claim 2
Dependent Claim
148 words
A substrate tap incorporated in an integrated circuit comprising a plurality of transistors formed in isolated device regions where the transistors will be formed in a substrate material comprising a layer of N-type material over a layer of P-type substrate material, the isolated device regions being defined by isolating slots surrounding said regions and extending down through said N-type material and into said P-type material, the trench for said substrate tap extending down to said P-type material, an oxide layer lining the sidewalls of trench, a doped polysilicon layer covering the sides and bottom of said trench, and a doped implant or diffused region formed at the base of and in contact with the bottom of said substrate tap to establish contact between said tap and said substrate, and means for connecting the substrate beneath said devices to a negative potential to isolate the devices on said substrate.
Claim 3
Dependent Claim
25 words
A substrate tap as claimed in Claim 1 including a silicide layer formed over said polysilicon layer to enhance contact to said doped implant region.
Claim 4
Dependent Claim
139 words
An integrated circuit having a plurality of substrate taps formed therein, the substrate tap being formed simultaneously with isolation slots defining slots defining tubs in a substrate comprising a layer of P-type substrate material having a layer of N+ type material defining a buried layer on said substrate, and an N-type epitaxial layer over said buried layer, the trench for said substrate tap extending down to said P-type material, an oxide layer lining the sidewalls of trench, a doped poly silicon layer covering the sides and bottom of said trench, and a doped implant region formed at the base of and in contact with the bottom of said substrate tap to establish contact between said tap and said substrate, and means for connecting the substrate beneath said devices to a negative potential to isolate the devices on said substrate.
Claim 5
Dependent Claim
139 words
An integrated circuit having a plurality of substrate taps formed therein, the substrate tap being formed simultaneously with isolation slots defining slots defining tubs in a substrate comprising a layer of P-type substrate material having a layer of N+ type material defining a buried layer on said substrate, and an N-type epitaxial layer over said buried layer, the trench for said substrate tap extending down to said P-type material, an oxide layer lining the sidewalls of trench, a doped poly silicon layer covering the sides and bottom of said trench, and a doped implant region formed at the base of and in contact with the bottom of said substrate tap to establish contact between said tap and said substrate, and means for connecting the substrate beneath said devices to a negative potential to isolate the devices on said substrate.
Claim 6
Dependent Claim
25 words
A substrate tap as claimed in Claim 3 including a silicide layer formed over said polysilicon layer to enhance contact to said doped implant region.
Claim 7
Dependent Claim
87 words
A process for fabricating a substrate tap in an integrated circuit comprising a plurality of bipolar transistors defining device regions where the bipolar transistors will be formed in a substrate comprising a layer of N-type material over a layer of P-type substrate material by formation of an isolation slits surrounding said region extending down through said N-type material to said P-type material, substantially simultaneously with the formation of said slit forming said substrate tap by the steps of cutting trenches for said slit and said substrate tap.
Claim 8
Dependent Claim
87 words
A process for fabricating a substrate tap in an integrated circuit comprising a plurality of bipolar transistors defining device regions where the bipolar transistors will be formed in a substrate comprising a layer of N-type material over a layer of P-type substrate material by formation of an isolation slits surrounding said region extending down through said N-type material to said P-type material, substantially simultaneously with the formation of said slit forming said substrate tap by the steps of cutting trenches for said slit and said substrate tap.
Claim 9
Dependent Claim
52 words
A method as in Claim 5 including the steps following formation of said trench oxide of anisotropically etching said oxide to etch away oxide from the bottom of said trench without removing said oxide from the sidewalls of said trench, and implanting said doped region through the open bottom of said trench.
Claim 10
Dependent Claim
40 words
A method as in Claim 5 including the step of forming said doped region by heating said doped polysilicon layer to drive the doping material from said polysilicon layer into said substrate to form the doped region in the substrate.
Claim 11
Dependent Claim
37 words
A method as in Claim 5 comprising the further step of forming a silicide layer over the surface of said doped polysilicon layer to enhance contact through said polysilicon to said doped implant region and said substrate.
Claim 12
Dependent Claim
55 words
A method as in Claim 5 including the further step of protecting said P-doped polysilicon from later processing to form active devices comprising the steps of spinning or photoresist to fill said substrate taps and exposing said photoresist to insulate said P-doped polysilicon from a layer of N-doped polysilicon used to form said active devices.
Claim 13
Independent Claim
183 words
A method of producing an integrated circuit having a plurality of substrate taps, the substrate taps being formed simultaneously with isolation slits defining tubs in a substrate comprising a layer of P-type substrate material having a layer of N+ type material defining a buried layer on said substrate and an N- type epitaxial layer over said buried layer, said slits and said taps being formed by steps comprising cutting trenches for said slits and said substrate tap, forming an oxide layer over said substrate to line said slit trench and sidewalls of said tap trench, depositing a doped polysilicon layer over said oxide in said substrate tap trench, forming a doped implant region of P-type material in said substrate at the base of and in contact with the bottom of said substrate tap to clearly establish contact between said tap and said substrate, and planarizing said substrate to prepare the surface of said substrate for formation of bipolar devices in tabs formed by said isolating trenches, the substrate beneath said devices being connected to the most negative potential available to isolate said devices.
Claim 14
Independent Claim
183 words
A method of producing an integrated circuit having a plurality of substrate taps, the substrate taps being formed simultaneously with isolation slits defining tubs in a substrate comprising a layer of P-type substrate material having a layer of N+ type material defining a buried layer on said substrate and an N- type epitaxial layer over said buried layer, said slits and said taps being formed by steps comprising cutting trenches for said slits and said substrate tap, forming an oxide layer over said substrate to line said slit trench and sidewalls of said tap trench, depositing a doped polysilicon layer over said oxide in said substrate tap trench, forming a doped implant region of P-type material in said substrate at the base of and in contact with the bottom of said substrate tap to clearly establish contact between said tap and said substrate, and planarizing said substrate to prepare the surface of said substrate for formation of bipolar devices in tabs formed by said isolating trenches, the substrate beneath said devices being connected to the most negative potential available to isolate said devices.
Claim 15
Dependent Claim
40 words
A method as in Claim 10 including the steps following formation of said trench oxide of anisotropically etching said oxide to etch away oxide from the bottom of said trench without removing said oxide from the sidewalls of said trench.
Claim 16
Dependent Claim
56 words
A method as in Claim 10 including the step of forming said doped region by doping the portion of said polysilicon layer in the bottom of said substrate tap trench and heating said doped polysilicon layer to drive the doping material from said polysilicon layer into said substrate to form the doped region in the substrate.
Claim 17
Dependent Claim
37 words
A method as in Claim 12 comprising the further step of forming a silicide layer over the surface of said doped polysilicon layer to enhance contact through said polysilicon to said doped implant region and said substrate.
Claim 18
Dependent Claim
55 words
A method as in Claim 13 including the further step of protecting said P-doped polysilicon from later processing to form active devices comprising the steps of spinning or photoresist to fill said substrate taps and exposing said photoresist to insulate said P-doped polysilicon from a layer of N-doped polysilicon used to form said active devices.
References Cited (Backward Citations)
No citation records indexed.
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