US5361220A
Expired / Lapsed
US
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Discrete cosine transformation with reduced components
Assignee: Fujifilm Holdings Corp
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Filing: 1992-11-27
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Granted: 1994-11-01
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Expires: 2012-11-27
Abstract
Abstract A discrete cosine transformation processor includes first and second one-dimensional discrete cosine transformation circuits, a pre-processing circuit connected to the input of the one-dimensional discrete cosine processing circuit, and a post-processing circuit connected to the output of the one-dimensional discrete cosine processing circuit. The pre-processing circuit of the first one-dimensional discrete cosine processing circuit and the post-processing circuit of said second one-dimensional discrete cosine transformation circuit includes a shared first butterfly circuit, and the post-processing circuit of the first one-dimensional discrete cosine transformation circuit and the pre-processing circuit of the second one-dimensional discrete cosine transformation circuit includes a shared second butterfly circuit. A look-up table is used for two bits of each of two elements to a DCT matrix. The shared portion of the look-up tables can be extended for use with the forward and inverse DCT processing. A discrete cosine transformation processor includes a calculation block for sequentially performing a calculation for a predetermined bit position of each of a set of input signals, an adder/subtracter connected to the calculation block, a shift register for sequentially storing the established portion of an output signal of the adder/subtracter, and a resister for sequentially storing the carry portion used for the addition/subtraction at the next calculation cycle.
Inventors
- 👤 Masanari Asano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 18:14
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10; G06F17/14; G06F17/147
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
198 words
A discrete cosine transformation processor comprising: a first one-dimensional discrete cosine transformation circuit comprising a first one-dimensional discrete cosine processing circuit, a first pre-processing circuit connected to an input of said first one-dimensional discrete cosine processing circuit, and a first post-processing circuit connected to an output of said first one-dimensional discrete cosine processing circuit; a transpose circuit; a second one-dimensional cosine transformation circuit comprising a second one-dimensional discrete cosine processing circuit, a second pre-processing circuit connected to an input of said second one-dimensional discrete cosine processing circuit, and a second post-processing circuit connected to an output of said second one-dimensional discrete cosine processing circuit, wherein said first pre-processing circuit of said first one-dimensional discrete cosine transformation circuit and said second post-processing circuit of said second one-dimensional discrete cosine transformation circuit comprises a shared first butterfly circuit, and said first post-processing circuit of said first one-dimensional discrete cosine transformation circuit and said second pre-processing circuit of said second one-dimensional discrete cosine transformation circuit comprises a shared second butterfly circuit, and wherein said transpose circuit is coupled to an output of said first one-dimensional discrete cosine transformation circuit and to an output of said second one-dimensional discrete cosine transformation circuit.
Claim 2
Dependent Claim
198 words
A discrete cosine transformation processor comprising: a first one-dimensional discrete cosine transformation circuit comprising a first one-dimensional discrete cosine processing circuit, a first pre-processing circuit connected to an input of said first one-dimensional discrete cosine processing circuit, and a first post-processing circuit connected to an output of said first one-dimensional discrete cosine processing circuit; a transpose circuit; a second one-dimensional cosine transformation circuit comprising a second one-dimensional discrete cosine processing circuit, a second pre-processing circuit connected to an input of said second one-dimensional discrete cosine processing circuit, and a second post-processing circuit connected to an output of said second one-dimensional discrete cosine processing circuit, wherein said first pre-processing circuit of said first one-dimensional discrete cosine transformation circuit and said second post-processing circuit of said second one-dimensional discrete cosine transformation circuit comprises a shared first butterfly circuit, and said first post-processing circuit of said first one-dimensional discrete cosine transformation circuit and said second pre-processing circuit of said second one-dimensional discrete cosine transformation circuit comprises a shared second butterfly circuit, and wherein said transpose circuit is coupled to an output of said first one-dimensional discrete cosine transformation circuit and to an output of said second one-dimensional discrete cosine transformation circuit.
Claim 3
Dependent Claim
64 words
A discrete cosine transformation processor according to claim 1, further comprising input means, coupled to said first one-dimensional discrete cosine transformation circuit, for receiving an input signal, wherein at least one of said first and second one-dimensional discrete cosine transformation circuits comprises means for storing a look-up table having an input coupled to two bits of each of two elements of said input signal.
Claim 4
Dependent Claim
43 words
A discrete cosine transformation processor according to claim 1, further comprising input means, coupled to said first one-dimensional discrete cosine transformation circuit, for receiving an input signal, wherein said discrete cosine transformation is performed on said input signal of an 8*8 block size.
Claim 5
Dependent Claim
66 words
A discrete cosine transformation processor according to claim 3, wherein each of said first and second one-dimensional discrete cosine transformation circuits comprises means for storing a look-up table having an input coupled to two bits of each of two elements of said input signal, and means for storing twelve look-up tables that are commonly used both for forward discrete cosine transformation and inverse discrete cosine transformation.
Claim 6
Dependent Claim
93 words
A discrete cosine transformation processor according to claim 1, wherein at least one of said first and second one-dimensional discrete cosine transformation circuit comprises: a calculation circuit for sequentially performing a discrete cosine transformation calculation for a predetermined bit position of each of a set of input signals; an adder/subtracter connected to the output of said calculation circuit; a shift register for sequentially storing a portion of an output signal of said adder/subtracter; and a register for sequentially storing a carry portion to be used for the addition/subtraction at a next calculation cycle.
Claim 7
Dependent Claim
58 words
A discrete cosine transformation processor comprising means for sampling two bits of each element of input data having a plurality of elements, and means for performing a forward/inverse cosine transformation (DCT) by using look-up tables, each look-up table being used for two bits of each of two elements of a forward DCT matrix and an inverse DCT matrix.
Claim 8
Dependent Claim
58 words
A discrete cosine transformation processor comprising means for sampling two bits of each element of input data having a plurality of elements, and means for performing a forward/inverse cosine transformation (DCT) by using look-up tables, each look-up table being used for two bits of each of two elements of a forward DCT matrix and an inverse DCT matrix.
Claim 9
Dependent Claim
42 words
A discrete cosine transformation processor according claim 6, wherein said discrete cosine transformation is performed on said input data having an 8*8 block size, and said look-up tables include twelve look-up tables commonly used for both the forward DCT and inverse DCT.
Claim 10
Dependent Claim
25 words
A discrete cosine transformation processor according to claim 7, further comprising a bit shift coefficient circuit for bypassing said input data of a predetermined element.
Claim 11
Dependent Claim
26 words
A discrete cosine transformation processor according to claim 6, further comprising a bit shift coefficient circuit for by passing said input data of a predetermined element.
Claim 12
Dependent Claim
79 words
A discrete cosine transformation processor for performing a discrete cosine transformation, comprising: a calculation circuit for sequentially performing a discrete cosine transformation calculation for a predetermined bit position of each of a set of input signals; an adder/subtracter connected to the output of said calculation circuit; a shift register for sequentially storing a portion of an output signal of said adder/subtracter; and a resister for sequentially storing a carry portion used for the addition/subtraction at a next calculation cycle.
Claim 13
Dependent Claim
79 words
A discrete cosine transformation processor for performing a discrete cosine transformation, comprising: a calculation circuit for sequentially performing a discrete cosine transformation calculation for a predetermined bit position of each of a set of input signals; an adder/subtracter connected to the output of said calculation circuit; a shift register for sequentially storing a portion of an output signal of said adder/subtracter; and a resister for sequentially storing a carry portion used for the addition/subtraction at a next calculation cycle.
Claim 14
Dependent Claim
204 words
A discrete cosine transformation processor with a products-summing circuit for performing a discrete cosine transformation, said products-summing circuit comprising: a plurality for calculation circuits, each including means for sequentially performing a discrete cosine transformation calculation for n bits (n is an interger except 0) from a lower bit at each cycle of a predetermined calculation procedure, and means for performing a discrete cosine transformation calculation for remaining upper m bits (m is an integer except 0) at an i-th cycle, (i is an interger except 0) of the calculation procedure; a first adder/subtracter for adding/subtracting the calculation result for the n bits obtained by each of said plurality of calculation circuits to/from the calculation result at the preceding cycle in accordance with a carry of the preceding cycle; a second adder/subtracter for adding/subtracting the calculation result for the m bits obtained by each of said plurality of calculation circuits to/from the calculation result at the preceding cycle in accordance with a carry of the preceding cycle; a register for sequentially storing the calculation result of said first adder/subtracter; and output means for adding the contents of said register to an output of said second adder/subtracter while aligning the bit positions, and outputting the result.
Claim 15
Dependent Claim
204 words
A discrete cosine transformation processor with a products-summing circuit for performing a discrete cosine transformation, said products-summing circuit comprising: a plurality for calculation circuits, each including means for sequentially performing a discrete cosine transformation calculation for n bits (n is an interger except 0) from a lower bit at each cycle of a predetermined calculation procedure, and means for performing a discrete cosine transformation calculation for remaining upper m bits (m is an integer except 0) at an i-th cycle, (i is an interger except 0) of the calculation procedure; a first adder/subtracter for adding/subtracting the calculation result for the n bits obtained by each of said plurality of calculation circuits to/from the calculation result at the preceding cycle in accordance with a carry of the preceding cycle; a second adder/subtracter for adding/subtracting the calculation result for the m bits obtained by each of said plurality of calculation circuits to/from the calculation result at the preceding cycle in accordance with a carry of the preceding cycle; a register for sequentially storing the calculation result of said first adder/subtracter; and output means for adding the contents of said register to an output of said second adder/subtracter while aligning the bit positions, and outputting the result.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-31 | 1998-05-02 | 1998-11-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-31 | 2002-05-02 | 2002-11-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-31 | 2006-05-02 | 2006-11-01 | $7700.00 | Window Closed / Lapsed |