US4336600A — Binary word processing method using a high-speed …

Claim 1

Independent Claim 223 words

An adding device for simultaneously adding a large number of words with each of said words being stored in an individual shift register and extracted on the serial output of said register, said device comprising: a transcoder device whose inputs are connected to the serial outputs of the plurality of said individual shift registers in which are stored said words to be added together, wherein said transcoder device is connected in order to present pure binary form outputs indicating the number of "one's" present on its input; a bistable flip-flop register connected to the output of said transcoder device; a parallel-bit add-divide circuit whose binary weight inputs are connected to the output of said flip-flop register. a separate shift register connected to the least significant bit output of said add-divide circuit; second separate register connected to the remaining outputs of said add-divide circuit which outputs a series of signals to correspondingly weighted inputs of said add-divide circuit, wherein said add-divide circuit calculates the half-sum of its inputs and provides a "one" output to said first separate register when said half-sum is not a whole number and wherein said add-divide circuit provides an output equal to the number of the whole part of said half-sum to said second separate register which represents the number of carried "one's" for use when calculating a subsequent half-sum.

Claim 2

Dependent Claim 223 words

An adding device for simultaneously adding a large number of words with each of said words being stored in an individual shift register and extracted on the serial output of said register, said device comprising: a transcoder device whose inputs are connected to the serial outputs of the plurality of said individual shift registers in which are stored said words to be added together, wherein said transcoder device is connected in order to present pure binary form outputs indicating the number of "one's" present on its input; a bistable flip-flop register connected to the output of said transcoder device; a parallel-bit add-divide circuit whose binary weight inputs are connected to the output of said flip-flop register. a separate shift register connected to the least significant bit output of said add-divide circuit; second separate register connected to the remaining outputs of said add-divide circuit which outputs a series of signals to correspondingly weighted inputs of said add-divide circuit, wherein said add-divide circuit calculates the half-sum of its inputs and provides a "one" output to said first separate register when said half-sum is not a whole number and wherein said add-divide circuit provides an output equal to the number of the whole part of said half-sum to said second separate register which represents the number of carried "one's" for use when calculating a subsequent half-sum.

Claim 3

Dependent Claim 107 words

An adding device in accordance with claim 10, wherein the transcoder device has a pyramidal structure with several processing stages, the input stage at the base of the pyramid comprising in parallel several elementary transcoder circuits each producing in pure binary form on its different outputs the number of "1's" for each binary weight of all the words applied to all its inputs, the outputs of at least two different transcoder circuits being grouped each time on the input of an add circuit, several stages of such add circuits being arranged in cascade, the last stage at the top of the pyramid comprising only one add circuit.

Claim 4

Dependent Claim 40 words

An adding device in accordance with claim 2, wherein the different successive stages constituting the transcoder device are connected together via bistable flip-flop registers with parallel inputs and outputs, all the registers being connected to a common clock signal generator.

Claim 5

Dependent Claim 198 words

An improved binary word processing method for simultaneously adding a large number of words with each of said words being stored in an individual shift register and extracted on the serial output of said register, comprising the steps of (1) extracting the least significant bits existing in said registers; (2) determining the number of "one's" amongst said extracted bits; (3) producing a number of carried "one's" related to the bits of immediately lesser weight wherein said number of carried "one's" is zero when said extracted bits are the least significant bits of said words; (4) adding to said determined number the number of carried "one's" relating to the bits of immediately lesser weight; (5) calculating the half-sum of said determined number and said carried number; (6) entering a "one" into a separate shift register when said half-sum is not a whole number and memorizing a number equal to the whole part of said half-sum; (7) extracting said memorized number as the number of carried "one's" for use when calculating the subsequent half-sum; and repeating steps 1 through 7 until the most significant bits of said registers have been extracted and said produced number of carried one's is zero.

Claim 6

Dependent Claim 198 words

An improved binary word processing method for simultaneously adding a large number of words with each of said words being stored in an individual shift register and extracted on the serial output of said register, comprising the steps of (1) extracting the least significant bits existing in said registers; (2) determining the number of "one's" amongst said extracted bits; (3) producing a number of carried "one's" related to the bits of immediately lesser weight wherein said number of carried "one's" is zero when said extracted bits are the least significant bits of said words; (4) adding to said determined number the number of carried "one's" relating to the bits of immediately lesser weight; (5) calculating the half-sum of said determined number and said carried number; (6) entering a "one" into a separate shift register when said half-sum is not a whole number and memorizing a number equal to the whole part of said half-sum; (7) extracting said memorized number as the number of carried "one's" for use when calculating the subsequent half-sum; and repeating steps 1 through 7 until the most significant bits of said registers have been extracted and said produced number of carried one's is zero.

Claim 7

Dependent Claim 37 words

The improved method of claim 4 wherein p words each comprising n bits are added together using one 16-input transcoder circuit requiring a maximum of n+r+s periods of clock signals, where 2 r ≦p<2 r+1 and ##EQU2##

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1985-06-21	1985-12-21	1986-06-22	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1989-06-21	1989-12-21	1990-06-22	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1993-06-21	1993-12-21	1994-06-22	$7700.00	Window Closed / Lapsed

Binary word processing method using a high-speed sequential adder

Abstract

Inventors

Bibliographic Details

Claims Analysis

References Cited (Backward Citations)

USPTO Annuity & Maintenance Windows

Assigned Categories & Tags

Assign Category Tag