US4293920A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Two-dimensional transform processor
Assignee: Lockheed Martin Corp
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Filing: 1979-09-04
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Granted: 1981-10-06
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Expires: 1999-09-04
Abstract
Abstract A processor capable of performing a two-dimensional transform on high speed serial sampled analog raster scanned data and outputing the results in a parallel fashion so as to provide for a data rate reduction. The processor utilizes a charge coupled device (CCD), a matrix multiplier to perform a one-dimensional transform on data samples from a serial to parallel converter. The data is switched into a set of matrix multipliers which perform another transformation whose results are summed in an accumulator to yield the desired two-dimensional transformed coefficients.
Inventors
- 👤 Pasquale A. Merola
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 21:32
CPC Classifications
G; G06; G06T; G06T1/00; G06T1/0007; G06G; G06G7/00; G06G7/12; G06G7/22; H; H04; H04N; H04N19/00; H04N19/60
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
224 words
A two-dimensional transform processor capable of sampling each pixel of raster scanned serial data every tp seconds comprising: a series to parallel data converter means which accepts N raster scanned serial data samples and transforms the order of said samples into a parallel order; a first matrix multiplier means capable of accepting data from said series to parallel data converter means in a parallel order every Ntp seconds and yielding N one-dimensional transformed data samples as output values every Ntp seconds; at least N switching means, each of said switching means having one input terminal and N output terminals, each input terminal of each of said switching means being connected to said first matrix multiplier so as to accept one of the N one-dimensional transformed data samples, said N output terminals of each of said N switching means having one data sample and N-1 zero valued samples; at least N second matrix multiplier means, each of said second matrix multiplier means having N input terminals and N output terminals, each of said N input terminals being connected to N output terminals of one of said N switching means, each of said N second matrix multiplier means computing N partial products every Ntp seconds; an accumulator means which accumulates N 2 partial products which comprise the two-dimensional transform of said raster scanned serial pixel samples.
Claim 2
Dependent Claim
224 words
A two-dimensional transform processor capable of sampling each pixel of raster scanned serial data every tp seconds comprising: a series to parallel data converter means which accepts N raster scanned serial data samples and transforms the order of said samples into a parallel order; a first matrix multiplier means capable of accepting data from said series to parallel data converter means in a parallel order every Ntp seconds and yielding N one-dimensional transformed data samples as output values every Ntp seconds; at least N switching means, each of said switching means having one input terminal and N output terminals, each input terminal of each of said switching means being connected to said first matrix multiplier so as to accept one of the N one-dimensional transformed data samples, said N output terminals of each of said N switching means having one data sample and N-1 zero valued samples; at least N second matrix multiplier means, each of said second matrix multiplier means having N input terminals and N output terminals, each of said N input terminals being connected to N output terminals of one of said N switching means, each of said N second matrix multiplier means computing N partial products every Ntp seconds; an accumulator means which accumulates N 2 partial products which comprise the two-dimensional transform of said raster scanned serial pixel samples.
Claim 3
Dependent Claim
116 words
The two-dimensional transform processor as set forth in claim 1 wherein said series to parallel data converter means further comprises: an input line which receives a video signal sample every clock cycle (tp seconds); a set of N analog delay lines, each said delay line having an input end connected to said input line and an output end, each of said delay lines being one sample shorter than the next, with the longest delay line being N samples long so that at the end of N clock cycles, N video signals which had been in a serial order on said input line are in a parallel order at the outputs of said N analog delay lines.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-10-05 | 1985-04-06 | 1985-10-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-10-05 | 1989-04-06 | 1989-10-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-10-05 | 1993-04-06 | 1993-10-06 | $7700.00 | Window Closed / Lapsed |