← Back to Patent Explorer
US3775753A Expired / Lapsed US ⏱️ 0.0 years remaining

Vector order computing system

Assignee: Texas Instruments Inc
•
Filing: 1971-01-04
•
Granted: 1973-11-27
•
Expires: 1991-01-04
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A computing system is specifically adapted for the performance of vector operations. A computing system takes two vector streams and orders the elements of those vector streams into a single ordered vector stream. Each vector stream is received in a different receiver register with each vector being clocked down through the computing system. The elements of the vector streams are compared and ordered into a single ordered vector stream.

Inventors

  • 👤 W Kastner

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 09:41
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10; G06F17/16; G06F7/00; G06F7/22; G06F7/36

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 285 words
A computing system for ordering a first vector stream having an array of elements and a second vector stream having an array of elements into a third vector stream having sets of ordered elements comprising, a. a first buffer register for receiving said first vector stream one element at a time, b. a second buffer register for receiving said first vector stream one element at a time, c. an output register for temporary storage of the ordered third vector stream one element at a time, d. a first receiver register for storage of said first vector stream from said first buffer register one element at a time, e. a second receiver register for storage of said second vector stream from said second buffer register one element at a time, f. a first temporary storage register, g. a second temporary storage register, h. first selection means selectively connected to said first receiver register and said first temporary storage register for presenting the vector elements in said first temporary storage registers or said first receiver registers, i. second selection means selectively connected to said first temporary storage means and said second receiver register for presenting the vector elements in said first temporary storage register of said second receiver register, j. comparison means for comparing the vector elements presented in said first and second selection means according to predetermined criteria and transferring one of said vector elements into said first temporary storage register and one of said vector elements into said second temporary storage registers, and k. means responsive to said comparing means for transferring the vector element stored in said second temporary storage means to said output register as an element of said ordered third vector stream.
Claim 2
Dependent Claim 285 words
A computing system for ordering a first vector stream having an array of elements and a second vector stream having an array of elements into a third vector stream having sets of ordered elements comprising, a. a first buffer register for receiving said first vector stream one element at a time, b. a second buffer register for receiving said first vector stream one element at a time, c. an output register for temporary storage of the ordered third vector stream one element at a time, d. a first receiver register for storage of said first vector stream from said first buffer register one element at a time, e. a second receiver register for storage of said second vector stream from said second buffer register one element at a time, f. a first temporary storage register, g. a second temporary storage register, h. first selection means selectively connected to said first receiver register and said first temporary storage register for presenting the vector elements in said first temporary storage registers or said first receiver registers, i. second selection means selectively connected to said first temporary storage means and said second receiver register for presenting the vector elements in said first temporary storage register of said second receiver register, j. comparison means for comparing the vector elements presented in said first and second selection means according to predetermined criteria and transferring one of said vector elements into said first temporary storage register and one of said vector elements into said second temporary storage registers, and k. means responsive to said comparing means for transferring the vector element stored in said second temporary storage means to said output register as an element of said ordered third vector stream.
Claim 3
Dependent Claim 93 words
The computing system claimed in claim 1 including means responsive to said comparing means for selectively connecting said first temporary register to one of said selection means and one receiver registers to the other of said selection means to present an element from each of said first and second vector streams, said comparison means responsive to said selective correction for comparing said vector elements according to said predetermined criteria and transferring one of said vector elements into said first temporary register and one of said vector elements into said second temporary storage registers.

References Cited (Backward Citations)

US2987705A Cited
US2901732A Cited
US3248528A Cited
US3311892A Cited
US3343140A Cited
US3380029A Cited
US3541516A Cited
US3399383A Cited
US3428946A Cited
US3440611A Cited
US3508204A Cited
US3509542A Cited
US3573851A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-11-26 1977-05-28 1977-11-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-11-26 1981-05-28 1981-11-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-11-26 1985-05-28 1985-11-27 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag