MIS type capacitor having reduced change in capacitance when biased in forward and reverse directions

Claim 1

A MIS capacitor in a semiconductor integrated circuit device, comprising: a semiconductor substrate including an island region; a first semiconductor layer of one conductivity type, provided in said island region, having first and second ends opposed to each other; an insulating layer provided over said first semiconductor layer; a first electrode provided on said insulating layer; a second semiconductor layer of an opposite conductivity type formed in said island region to provide a PN junction with said first end of said first semiconductor layer; said PN junction intersecting an upper surface of said island region to be spaced apart from an edge of said first electrode; a second electrode being in contact with said second semiconductor layer; a third electrode attached to said second end of said first semiconductor layer; and means for producing a voltage drop across said PN junction when a reverse voltage is applied between said first and second electrodes; wherein said voltage drop is given by electrically connecting said second electrode to said third electrode through an external resistor.