Semiconductor integrated amplifier

Claim 2

An amplifier circuit having a p-channel type MISFET and an n-channel type MISFET which are integrated in a single semiconductor substrate, a load resistance connected between the drain regions of said MISFETs, a power source to which said MISFETs are connected in series, and a capacitance through which the gates of said MISFETs are connected to each other, characterized by comprising said capacitance having one terminal constituted by a well formed in said semiconductor substrate and another electrode constituted by a gate electrode formed on the surface of said well, said gate electrode and said semiconductor substrate being connected to the high voltage side of the power supply while said well is connected to the low voltage side of the power supply.

Claim 3

An amplifier circuit as set forth in claim 1, wherein said gate electrode is connected to the gate of one of said MISFET connected to the high voltage side of the power supply, while said well is connected to the gate of the other MISFET connected to the low voltage side of the power supply.

Claim 4

An amplifier circuit according to claim 1, wherein the capacitance is formed in the substrate between the MISFETs.

Claim 5

A semiconductor integrated circuit comprising a semiconductor body having a major surface of a first conductivity type, a first and a second semiconductor region of the second conductivity type formed in the major surface of said body, a first conductivity type MIS transistor formed at the surface of said first region, a second conductivity type MIS transistor formed at the major surface of said body separated from the first and second regions, an insulating film formed on the surface of said second region, a conductive layer formed on the insulating film, means for connecting said second region to the gate electrode of said first conductivity type MIS transistor, and means for connecting said conductive layer to the gate electrode of said second conductivity type MIS transistor, so as to couple both gate electrodes with a capacitor, wherein said first region and said semiconductor body are respectively connected to first and second power source terminals coupled to first and second potentials, respectively, for energizing said first and second conducitivity type MIS transistors to back bias the junction formed between the second region and the semiconductor body to reduce the parasitic capacitance between the second region and the semiconductor body.

Claim 6

A semiconductor integrated circuit comprising a semiconductor body having a major surface of a first conductivity type, a first and a second semiconductor region of the second conductivity type formed in the major surface of said body, a first conductivity type MIS transistor formed at the surface of said first region, a second conductivity type MIS transistor formed at the major surface of said body separated from the first and second regions, an insulating film formed on the surface of said second region, a conductive layer formed on the insulating film, means for connecting said second region to the gate electrode of said first conductivity type MIS transistor, and means for connecting said conductive layer to the gate electrode of said second conductivity type MIS transistor, so as to couple both gate electrodes with a capacitor, wherein said first region and said semiconductor body are respectively connected to first and second power source terminals coupled to first and second potentials, respectively, for energizing said first and second conducitivity type MIS transistors to back bias the junction formed between the second region and the semiconductor body to reduce the parasitic capacitance between the second region and the semiconductor body.

Claim 7

A semiconductor integrated circuit as set forth in claim 3, said first and second conductivity type MIS transistors are p-channel and n-channel MIS transistors, respectively.

Claim 8

A semiconductor integrated circuit according to claim 4, wherein the first conductivity type is N-type, the second conductivity type is P-type, and the second potential coupled to the second conductivity type MIS transistor is the high voltage side of a power source which high voltage side is greater than the first potential.

Claim 9

A semiconductor integrated circuit according to claim 4, wherein the first conductivity type is P-type, the second conductivity type is N-type, and the first potential coupled to the first conductivity type MIS transistor is the high voltage side of a power source which high voltage side is greater than the second potential.

Claim 10

A semiconductor integrated circuit according to claim 4, wherein said second region is formed in the semiconductor body between the MIS transistors.

Claim 11

A semiconductor integrated circuit according to claim 3, wherein the first conductivity type MIS includes a source and a drain region of the first conductivity type formed in the surface of the first region, the second conductivity type MIS includes a source and a drain region of the second conductivity type formed in the major surface of the semiconductor body, and further comprising means for connecting the drain region of said first conductivity type MIS transistor to the drain region of said second conductivity type MIS transistor, a first power source terminal connected to said first region and said source region formed in the first region to supply a first potential to said first region, a second power source terminal connected to said semiconductor body and said source region formed in the body to supply a second potential to said semiconductor body and the source region of the second conductivity type MIS transistor, first bias means for providing a first bias voltage between the gate electrode and source region of said first conductivity type MIS transistor, and second bias means for providing a second bias voltage between the gate electrode and source region of said second conductivity type MIS transistor, whereby the junction formed between said second region and said semiconductor body is back-baised by a potential difference between the second potential and a potential at gate electrode of said first conductivity type MIS transistor so as to reduce the parasitic capacitance of said junction.