US4100502A — Class B FET amplifier circuit

Claim 1

Independent Claim 135 words

An FET circuit comprising an amplifier stage and a waveform shaping stage; said amplifier stage including a first p-channel FET and a first n-channel FET, means for biasing the gate of each of said FETs at a dc level nearly equal to its drain potential, (means for setting the potential differential between the source and the drain of each of said FETS at a voltage nearly equal to its threshold voltage;) and means for supplying a linear input signal to said gates through respective capacitors; and said waveform shaping stage comprising means for converting a linear signal into a digital signal including a second p-channel FET having a gate coupled to the drain of said first p-channel FET, and a second n-channel FET having a gate coupled to the drain of said first n-channel FET.

Claim 2

Dependent Claim 135 words

An FET circuit comprising an amplifier stage and a waveform shaping stage; said amplifier stage including a first p-channel FET and a first n-channel FET, means for biasing the gate of each of said FETs at a dc level nearly equal to its drain potential, (means for setting the potential differential between the source and the drain of each of said FETS at a voltage nearly equal to its threshold voltage;) and means for supplying a linear input signal to said gates through respective capacitors; and said waveform shaping stage comprising means for converting a linear signal into a digital signal including a second p-channel FET having a gate coupled to the drain of said first p-channel FET, and a second n-channel FET having a gate coupled to the drain of said first n-channel FET.

Claim 3

Dependent Claim 114 words

An amplifier circuit comprising a complementary inverter including a first FET of a first conductivity type connected to a first source potential, a second FET of a second conductivity type connected to a second source potential, and an input terminal connected to the gates of said first and second FETs, the circuit comprising: a series connection of first and second load resistors connected between said first and second FETs; a respective bias resistor connected between the gate and the drain of each of said first and second FETs; a respective capacitor connected between the input terminal and the gate of each of said FETs; and output means connected to the drains of said FETs.

Claim 4

Dependent Claim 114 words

An amplifier circuit comprising a complementary inverter including a first FET of a first conductivity type connected to a first source potential, a second FET of a second conductivity type connected to a second source potential, and an input terminal connected to the gates of said first and second FETs, the circuit comprising: a series connection of first and second load resistors connected between said first and second FETs; a respective bias resistor connected between the gate and the drain of each of said first and second FETs; a respective capacitor connected between the input terminal and the gate of each of said FETs; and output means connected to the drains of said FETs.

Claim 5

Dependent Claim 24 words

The amplifier circuit according to claim 2, in which said output means comprises a terminal connected to the interconnection point of said load resistors.

Claim 6

Dependent Claim 28 words

The amplifier circuit according to claim 2, in which said output means comprises a pair of terminals connected to the drains of said first and second FETs, respectively.

Claim 7

Dependent Claim 90 words

An amplifier circuit comprising, in combination, first and second operating voltage terminals of different potential level; first and second field effect transistors (FET) of complementary conductivity type, each having a source, a gate and a drain, the sources of said complementary FETs being connected to said first and second operating voltage terminals respectively, the gates of said complementary FETs being ac-coupled to an input terminal; and a resistor connected between the drains of said complementary FETs, the connection between said resistor and said complementary FETs serving as an output terminal.

Claim 8

Dependent Claim 90 words

An amplifier circuit comprising, in combination, first and second operating voltage terminals of different potential level; first and second field effect transistors (FET) of complementary conductivity type, each having a source, a gate and a drain, the sources of said complementary FETs being connected to said first and second operating voltage terminals respectively, the gates of said complementary FETs being ac-coupled to an input terminal; and a resistor connected between the drains of said complementary FETs, the connection between said resistor and said complementary FETs serving as an output terminal.

Claim 9

Dependent Claim 52 words

The amplifier circuit according to claim 5, further comprising a biasing resistor connected between the gate and the drain of at least one of said first and second FETs, the bias potential between the gate and the source of said FET being determined at a potential nearly equal to its threshold voltage.

Claim 10

Dependent Claim 60 words

The amplifier circuit according to claim 5, further comprising a first and a second biasing resistors connected between the gates and the drains of said first and second FETs respectively, and an ac coupling capacitor connected between the gate of said first FET and said input terminal, the input terminal being connected directly to the gate of said second FET.

Claim 11

Dependent Claim 72 words

A complementary push-pull amplifier comprising: a p-channel FET having a source coupled to a positive power source terminal, a gate and a drain; an n-channel FET having a source coupled to a negative power source terminal, a gate and a drain; resistive means coupled between said drains of said FETs and; means for applying an a.c. input signal to said gates of said FETs to operate said FETs in a push-pull mode.

Claim 12

Dependent Claim 72 words

A complementary push-pull amplifier comprising: a p-channel FET having a source coupled to a positive power source terminal, a gate and a drain; an n-channel FET having a source coupled to a negative power source terminal, a gate and a drain; resistive means coupled between said drains of said FETs and; means for applying an a.c. input signal to said gates of said FETs to operate said FETs in a push-pull mode.

Claim 13

Dependent Claim 30 words

The amplifier as defined in claim 8 further including means for applying to the gate of one of said FETs a bias voltage substantially equal to its drain d.c. potential.

Claim 14

Dependent Claim 40 words

The amplifier as defined claim 9 further including means for applying to the gate of the other FET a bias voltage substantially equal to its drain d.c. potential, and a d.c. blocking capacitor coupled between said gates of said FETs.

Claim 15

Dependent Claim 134 words

A complementary push-pull comprising a p-channel FET, an n-channel FET, resistive load means connected to at least one of said FETs, a resistive bias means coupled between the gate and drain of said one FET for applying a bias voltage substantially equal to the drain d.c. potential of said FET to said gate thereof, means for connecting said FETs and said resistive load means so that said resistive load means and the conduction paths between the sources and the drains of the respective FETs are connected in series and, means for applying an a.c. input signal to the gates of said FETs, the resistance of said load means being higher than the on-resistance of said one FET and the potential differential between the source and gate of said one FET approaching its threshold voltage.

Claim 16

Dependent Claim 134 words

A complementary push-pull comprising a p-channel FET, an n-channel FET, resistive load means connected to at least one of said FETs, a resistive bias means coupled between the gate and drain of said one FET for applying a bias voltage substantially equal to the drain d.c. potential of said FET to said gate thereof, means for connecting said FETs and said resistive load means so that said resistive load means and the conduction paths between the sources and the drains of the respective FETs are connected in series and, means for applying an a.c. input signal to the gates of said FETs, the resistance of said load means being higher than the on-resistance of said one FET and the potential differential between the source and gate of said one FET approaching its threshold voltage.

Claim 17

Dependent Claim 129 words

The amplifier as defined in claim 11 comprising a d.c. blocking capacitor coupled between the gates of said FETs, resistive bias means coupled between the gate and drain of the other FET of applying a bias voltage substantially equal to the drain d.c. potential of the other FET to the gate thereof and, output deriving means wherein said load means is coupled between the drains of both FETs so as to act as a common load for both FETs, the resistance of said load means being higher than the on-resistance of the other FET and the potential differential between the source and gate of the other FET approaching its threshold voltage, said output deriving means deriving at least one output from the node between the drains of both FETs.

Claim 18

Dependent Claim 50 words

The amplifier as defined in claim 12 in which a single capacitor is connected between the gates of both FETs, said a.c. input signal being directly applied to the gate of one of said FETs and being applied to the gate of the other by way of said single capacitor.

Claim 19

Dependent Claim 54 words

A complementary FET circuit comprising an amplifier stage and a succeeding state, each being comprised of complementary FETs, said amplifier stage including means for producing two output signals having d.c. potentials different from each other in response to an input signal, said succeeding stage having two input terminals for receiving said two output signals.

Claim 20

Dependent Claim 54 words

A complementary FET circuit comprising an amplifier stage and a succeeding state, each being comprised of complementary FETs, said amplifier stage including means for producing two output signals having d.c. potentials different from each other in response to an input signal, said succeeding stage having two input terminals for receiving said two output signals.

Claim 21

Dependent Claim 71 words

The FET circuit as defined in claim 14, in which each of said stages comprises a p-channel FET and an n-channel FET, the respective potential differential between the source and the drain of each FET in said amplifier stage is supplied between the source and the gate of the corresponding FET in said succeeding stage, respectively, and said respective potential differential is substantially equal to the threshold voltage of that FET.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1981-07-10	1982-01-09	1982-07-11	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1985-07-10	1986-01-09	1986-07-11	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1989-07-10	1990-01-09	1990-07-11	$7700.00	Window Closed / Lapsed

Class B FET amplifier circuit

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