Memory testing system with algorithmic test data generation

Claim 1

A system for providing test data for testing a semiconductor memory having a plurality of input pins, comprising: control means for supplying control signals; at least one prechannel for developing test data in a predetermined manner responsive to said control signals, each of said at least one prechannel comprising: start means for providing a seed data pattern in response to one of said control signals; configuration means for providing a desired configuration; generation means for successively developing generated data patterns, in response to another one of said control signals, beginning from said seed data pattern, such that every distinct data pattern of said seed data pattern is successively developed in a forward sequence without repetition of any distinct data pattern and, subsequently, said distinct data patterns are successively developed in a reverse sequence relative to said forward sequence; and selection means for successively selecting data from said seed data pattern and each of said generated data patterns, according to said desired configuration, for developing said test data; and a plurality of channels, each channel receiving test data from a corresponding one of said at least one prechannel, and each channel applying said test data to a corresponding one of said plurality of input pins; wherein each of said at least one prechannel provides test data to at least two corresponding channels such that each of said at least one prechannel is in close proximity to the channels corresponding thereto.

Claim 2

A system for providing test data for testing a semiconductor memory having a plurality of input pins, comprising: control means for supplying control signals; at least one prechannel for developing test data in a predetermined manner responsive to said control signals, each of said at least one prechannel comprising: start means for providing a seed data pattern in response to one of said control signals; configuration means for providing a desired configuration; generation means for successively developing generated data patterns, in response to another one of said control signals, beginning from said seed data pattern, such that every distinct data pattern of said seed data pattern is successively developed in a forward sequence without repetition of any distinct data pattern and, subsequently, said distinct data patterns are successively developed in a reverse sequence relative to said forward sequence; and selection means for successively selecting data from said seed data pattern and each of said generated data patterns, according to said desired configuration, for developing said test data; and a plurality of channels, each channel receiving test data from a corresponding one of said at least one prechannel, and each channel applying said test data to a corresponding one of said plurality of input pins; wherein each of said at least one prechannel provides test data to at least two corresponding channels such that each of said at least one prechannel is in close proximity to the channels corresponding thereto.