EP0254017A2
Expired / Lapsed
EP
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Calibrated automatic test system
Assignee: Credence Systems Corp
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Filing: 1987-06-12
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Granted: —
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Expires: 2007-06-12
Abstract
Abstract A calibrated automatic test system includes a test station for generating digital test function codes and a test head containing a plurality of I/O pins for connection to a device under test. Each I/O pin includes a pin electronics circuit responsive to the digital test function codes for providing test signals to the device under test. The pin electronics circuits are inexpensive CMOS IC's and lack the accuracy needed to test VLSI devices at the frequencies of interest. An external calibration unit is connected to each I/O pin and data measurements are taken which represent the performance of the CMOS IC's. The data measurements are converted to calibrated function codes representing desired data values which are then stored in correction memory circuits which respond to nominal digital test function codes and substitute in their places calibrated function codes which are then supplied to the pin electronics circuits.
Inventors
- 👤 Donald F. Murray
- 👤 Steven K. Sullivan
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 21:51
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31903; G01R31/31908; G01R31/3191
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
88 words
An automatic test system for testing an electronic device comprising: (a) a programmable test station, including a test head having a plurality of output pin means for connection to a device under test; (b) CMOS integrated circuit means associated with each of said output pin means for providing test signals to said device under test; and (c) external calibration means selectively connectable to each of said output pin means for receiving said test signals and for deriving therefrom error correction signals for calibrating said CMOS integrated circuit means.
Claim 2
Dependent Claim
88 words
An automatic test system for testing an electronic device comprising: (a) a programmable test station, including a test head having a plurality of output pin means for connection to a device under test; (b) CMOS integrated circuit means associated with each of said output pin means for providing test signals to said device under test; and (c) external calibration means selectively connectable to each of said output pin means for receiving said test signals and for deriving therefrom error correction signals for calibrating said CMOS integrated circuit means.
Claim 3
Dependent Claim
54 words
The automatic test system of claim 1 wherein said test signals are provided in response to test function digital codes from said test station, and further including error correction memory means responsive to said error correction signals for altering said test function digital codes, thereby producing corrected test signals at said output pin means.
Claim 4
Dependent Claim
34 words
The automatic test system of claim 1 wherein said external calibration means is portable and includes X-Y positioning means for selectively connecting said external calibration means to selected ones of said output pin means.
Claim 5
Dependent Claim
106 words
An automatic test system for testing electrical devices comprising: (a) a programmable test station for generating test functions represented by digital test codes; (b) test head means connected to said test station for providing output means for connection to a device under test; (c) a plurality of circuit means, one for each output means of said test head means for providing test data to said device under test in response to said digital test codes; and (d) calibration means selectively connectable to said test head means for deriving calibrated digital test codes to be selectively substituted for said digital test codes generated by said test station.
Claim 6
Dependent Claim
106 words
An automatic test system for testing electrical devices comprising: (a) a programmable test station for generating test functions represented by digital test codes; (b) test head means connected to said test station for providing output means for connection to a device under test; (c) a plurality of circuit means, one for each output means of said test head means for providing test data to said device under test in response to said digital test codes; and (d) calibration means selectively connectable to said test head means for deriving calibrated digital test codes to be selectively substituted for said digital test codes generated by said test station.
Claim 7
Dependent Claim
27 words
The automatic test system of claim 4, further including error correction memory means associated with each of said circuit means for storing said calibrated digital test codes.
Claim 8
Dependent Claim
33 words
The automatic test system of claim 4 wherein said calibration means comprises an external portable unit including positioning means for selectively connecting said unit to each output means of said test head means.
Claim 9
Dependent Claim
44 words
The automatic test system of claim 5 wherein said calibration means comprises means for measuring test data provided to each of said output means by said circuit means in response to said digital test codes, and further including memory means for storing said data.
Claim 10
Dependent Claim
71 words
The automatic test system of claim 7, further including means for looking up in said memory means data representing predetermined performance characteristics of said circuit means, for deriving said calibrated digital test codes therefrom, and for storing said calibrated digital test codes in said correction memory means whereby the generation of predetermined ones of said digital test codes triggers said correction memory means to substitute said calibrated digital test codes therefor.
Claim 11
Dependent Claim
15 words
The automatic test system of claim 8 wherein said circuit means comprise CMOS integrated circuits.
Claim 12
Dependent Claim
81 words
An automatic test system for testing electrical devices comprising: (a) a programmable test station; (b) a multipin connector controlled by said test station, said multipin connector including electronic circuits for each pin of said connector for executing predetermined test functions; (c) correction memory means associated with each of said electronic circuits for providing codes representing calibrated test functions; and (d) external calibration means selectively connectable to said multipin connector for determining said codes to be stored in said correction memory means.
Claim 13
Dependent Claim
81 words
An automatic test system for testing electrical devices comprising: (a) a programmable test station; (b) a multipin connector controlled by said test station, said multipin connector including electronic circuits for each pin of said connector for executing predetermined test functions; (c) correction memory means associated with each of said electronic circuits for providing codes representing calibrated test functions; and (d) external calibration means selectively connectable to said multipin connector for determining said codes to be stored in said correction memory means.
Claim 14
Dependent Claim
27 words
The automatic test system of claim 10 wherein said external calibration means comprises X-Y probe means for connection to said multipin connector, one pin at a time.
Claim 15
Dependent Claim
38 words
The automatic test system of claim 11 wherein said external calibration means includes means for measuring preselected data parameters of signals generated by said electronic circuits and for causing said data parameters to be stored in a memory.
Claim 16
Dependent Claim
44 words
The automatic test system of claim 12, further including computer means for determining function codes for said data parameters and for loading preselected ones of said function codes into said correction memory means to replace nominal function codes generated by said programmable test station.
Claim 17
Dependent Claim
36 words
The automatic test system of claim 13 wherein said correction memory means includes multiplexing means for permitting selection between the contents of said correction memory means and uncorrected function codes generated by said programmable test station.
Claim 18
Independent Claim
117 words
A method of calibrating an automatic test system for testing electrical devices comprising the steps of: (a) connecting a calibration circuit including a memory to an output of said automatic test system; (b) initiating a plurality of test functions, each having a digital code, from said automatic test system; (c) measuring with said calibration circuit the data produced at said output by each of said test functions and storing said data in said memory; (d) determining a desired data value for at least one of said test functions; (e) looking up in said memory a measured data value corresponding to the said desired data value; and (f) determining the digital code that produced said measured data value.
Claim 19
Independent Claim
117 words
A method of calibrating an automatic test system for testing electrical devices comprising the steps of: (a) connecting a calibration circuit including a memory to an output of said automatic test system; (b) initiating a plurality of test functions, each having a digital code, from said automatic test system; (c) measuring with said calibration circuit the data produced at said output by each of said test functions and storing said data in said memory; (d) determining a desired data value for at least one of said test functions; (e) looking up in said memory a measured data value corresponding to the said desired data value; and (f) determining the digital code that produced said measured data value.
Claim 20
Dependent Claim
27 words
The method of claim 12, further including as step (g) placing said digital code in a correction memory associated with said output of said automatic test system.
Claim 21
Dependent Claim
29 words
The method of claim 16 wherein said automatic test system includes a plurality of outputs and steps (a) through (g) are serially repeated for each one of said outputs.
References Cited (Backward Citations)
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