Macrocell with product-term cascade and improved flip flop utilization

Claim 2

A programmable logic circuit comprising: a plurality of input lines; a dedicated line; a flip flop having a flip flop data input terminal and a flip flop output terminal; a first logic gate receiving input signals from said plurality of input lines, said first logic gate having a first logic gate output terminal; and a cascade circuit having first and second programmable states, said cascade circuit connecting said first logic gate output terminal to said flip flop data input terminal when in said first programmable state, said cascade circuit connecting said first logic gate output terminal to an input terminal of a second logic gate and connecting said dedicated line to said flip flop data input terminal when in said second programmable state.

Claim 3

A programmable logic circuit as in claim 1 in which said dedicated line serves as a flip flop reset signal when said cascade circuit is in said first programmable state.

Claim 4

A programmable logic circuit as in claim 1 in which said dedicated line serves as a flip flop set signal when said cascade circuit is in said first programmable state.

Claim 5

A programmable logic circuit as in claim 1 further comprising: a third logic gate having an output terminal; means for connecting said output terminal of said upstream logic gate to one of said plurality of input lines.

Claim 6

A programmable logic circuit as in claim 4 in which said means for connecting said output terminal of said third logic gate to one of said plurality of input lines and said cascade circuit operate together to form a cascade circuit to pass signals from said third logic gate to said second logic gate.

Claim 7

The programmable logic circuit according to claim 1, further comprising a clock selection circuit having a clock output terminal, said clock selection circuit providing a clock signal at said clock output terminal to a clock signal terminal of said flip flop, wherein said clock signal is programmably selected from a plurality of clock signals.

Claim 8

The programmable logic circuit according to claim 1 further comprising an inverter connected to said flip flop output terminal.

Claim 9

A programmable logic circuit comprising: a plurality of input lines; a dedicated line; a first logic gate receiving input signals from said plurality of input lines, said first logic gate having a first logic gate output terminal; a flip flop having a flip flop data input terminal, a clock input terminal and a flip flop output terminal; a first multiplexer having a control terminal and two input terminals, the first input terminal connected to said first logic gate output terminal, the second input terminal connected to a reference level, said first multiplexer having an output terminal connected to an input terminal of a second logic gate; a second multiplexer having a control terminal and two input terminals, the first input terminal connected to said first logic gate output terminal, the second input terminal connected to said dedicated line, said second multiplexer having an output terminal connected to said flip flop data input terminal; a cascade control circuit connected to the control terminals of said first and second multiplexers, said cascade control circuit having first and second programmable states, said first programmable state: causing said first multiplexer to select said reference level, and causing said second multiplexer to select said first logic output line; said second programmable state: causing said first multiplexer to select said first logic gate output line, and causing said second multiplexer to select said dedicated line.

Claim 10

A programmable logic circuit comprising: a plurality of input lines; a dedicated line; a first logic gate receiving input signals from said plurality of input lines, said first logic gate having a first logic gate output terminal; a flip flop having a flip flop data input terminal, a clock input terminal and a flip flop output terminal; a first multiplexer having a control terminal and two input terminals, the first input terminal connected to said first logic gate output terminal, the second input terminal connected to a reference level, said first multiplexer having an output terminal connected to an input terminal of a second logic gate; a second multiplexer having a control terminal and two input terminals, the first input terminal connected to said first logic gate output terminal, the second input terminal connected to said dedicated line, said second multiplexer having an output terminal connected to said flip flop data input terminal; a cascade control circuit connected to the control terminals of said first and second multiplexers, said cascade control circuit having first and second programmable states, said first programmable state: causing said first multiplexer to select said reference level, and causing said second multiplexer to select said first logic output line; said second programmable state: causing said first multiplexer to select said first logic gate output line, and causing said second multiplexer to select said dedicated line.

Claim 11

A programmable logic circuit as in claim 8 in which said first logic gate also receives input signals from an output terminal of a third logic gate.

Claim 12

A programmable logic circuit as in claim 8 further comprising a third multiplexer having: a first input terminal connected to said dedicated line; a second input terminal connected to a reference voltage level; a control terminal connected to said cascade control circuit; and an output terminal connected to one of reset and set inputs of said flip flop; where in said first state said control circuit connects said dedicated line to said one of reset and set inputs of said flip flop, and in said second state said control circuit connects said reference level to said reset or set input of said flip flop.

Claim 13

A structure for a programmable logic circuit comprising: a plurality of macrocells each having: product term input signals; a logic gate which receives at least said product term input signals and generates an output signal therefrom; a flip flop having an input terminal; and a multiplexer having a first state and a second state, wherein said first state directs said output signal to said flip flop input terminal and said second state directs another signal to said flip flop input terminal and directs said output signal to a logic gate of another macrocell as an input signal thereof; and in which said another signal directed to said flip flop input terminal comprises a product term output signal from an AND array.

Claim 14

A structure for a programmable logic circuit comprising: a plurality of macrocells each having: product term input signals; a logic gate which receives at least said product term input signals and generates an output signal therefrom; a flip flop having an input terminal; and a multiplexer having a first state and a second state, wherein said first state directs said output signal to said flip flop input terminal and said second state directs another signal to said flip flop input terminal and directs said output signal to a logic gate of another macrocell as an input signal thereof; and in which said another signal directed to said flip flop input terminal comprises a product term output signal from an AND array.