MOS transistor with an integrated protection zener diode

Claim 2

A lateral MOS transistor, comprising: a substrate including a first low-doped surface layer of a first conductivity type substantially coating a second more highly-doped underlying layer of the first conductivity type; a drain region of a second conductivity type formed in the first surface layer; a source region of the second conductivity type formed in the first surface layer; a substrate contacting region formed in the first surface layer; and a region of the second conductivity type extending through the surface layer from a portion of the drain region to the underlying layer.

Claim 3

The MOS transistor of claim 1, wherein the source region, the drain region, and the substrate contacting region are formed in the first surface layer at a surface of the first surface layer.

Claim 4

The MOS transistor of claim 2, wherein the region of the second conductivity type extending through the first surface layer from a portion of the drain region to the second underlying layer comprises a highly-doped region of the second conductivity type.

Claim 5

The MOS transistor of claim 3, wherein the first conductivity type comprises P-type.

Claim 6

The MOS transistor of claim 4, wherein the second conductivity type comprises N-type.

Claim 7

The MOS transistor of claim 3, wherein the first conductivity type comprises N-type.

Claim 8

The MOS transistor of claim 6, wherein the second conductivity type comprises P-type.

Claim 9

The MOS transistor of claim 1, wherein the transistor is used as an output stage of a MOS type integrated circuit.

Claim 10

The MOS transistor of claim 1, wherein the transistor is constructed as an integrated circuit.

Claim 11

The MOS transistor of claim 1, wherein the substrate contacting region and the source region are interconnected.

Claim 12

A MOS integrated circuit output stage, comprising: a first lateral MOS transistor having a first source terminal coupled to a first voltage source; a second lateral MOS transistor having a second source terminal and a second drain terminal, the second source terminal coupled to a second voltage source; an output terminal coupled to the first drain terminal and the second drain terminal; wherein at least one of the first and second lateral MOS transistors comprises: a substrate including a first low-doped surface layer of a first conductivity type substantially coating a second more highly-doped underlying layer of the first conductivity type; a drain region of a second conductivity type formed in the first surface layer; a source region of the second conductivity type formed in the first surface layer; and a region of the second conductivity type extending through the surface layer from a portion of the drain region to the underlying layer.

Claim 13

A MOS integrated circuit output stage, comprising: a first lateral MOS transistor having a first source terminal coupled to a first voltage source; a second lateral MOS transistor having a second source terminal and a second drain terminal, the second source terminal coupled to a second voltage source; an output terminal coupled to the first drain terminal and the second drain terminal; wherein at least one of the first and second lateral MOS transistors comprises: a substrate including a first low-doped surface layer of a first conductivity type substantially coating a second more highly-doped underlying layer of the first conductivity type; a drain region of a second conductivity type formed in the first surface layer; a source region of the second conductivity type formed in the first surface layer; and a region of the second conductivity type extending through the surface layer from a portion of the drain region to the underlying layer.

Claim 14

The MOS integrated circuit of claim 11, further comprising: a substrate contacting region formed in the first surface layer and interconnected to the source region.

Claim 15

The MOS integrated circuit of claim 12, wherein the source region, the drain region, and the substrate contacting region are formed in the first surface layer at a surface of the first surface layer.

Claim 16

The MOS integrated circuit of claim 13, wherein the region of the second conductivity type extending through the first surface layer from a portion of the drain region to the second underlying layer comprises a highly-doped region of the second conductivity type.

Claim 17

The MOS integrated circuit of claim 14, wherein the first conductivity type comprises P-type.

Claim 18

The MOS integrated circuit of claim 15, wherein the second conductivity type comprises N-type.

Claim 19

The MOS integrated circuit of claim 14, wherein the first conductivity type comprises N-type.

Claim 20

The MOS integrated circuit of claim 17, wherein the second conductivity type comprises P-type.

Claim 21

A lateral MOS transistor including a substrate having a first low-doped surface layer of a first conductivity type coating a second more highly-doped underlying layer of the first conductivity type, a drain region of a second conductivity type formed in the first surface layer; a source region of the second conductivity type formed in the first surface layer, the improvement comprising: a region of the second conductivity type extending through the surface layer from a portion of the drain region to the underlying layer.

Claim 22

A lateral MOS transistor including a substrate having a first low-doped surface layer of a first conductivity type coating a second more highly-doped underlying layer of the first conductivity type, a drain region of a second conductivity type formed in the first surface layer; a source region of the second conductivity type formed in the first surface layer, the improvement comprising: a region of the second conductivity type extending through the surface layer from a portion of the drain region to the underlying layer.

Claim 23

The MOS transistor of claim 19, further comprising: a substrate contacting region formed in the first surface layer and interconnected to the source region.

Claim 24

The MOS transistor of claim 20, wherein the source region, the drain region, and the substrate contacting region are formed in the first surface layer at a surface of the first surface layer.

Claim 25

The MOS transistor of claim 21, wherein the region of the second conductivity type extending through the first surface layer from a portion of the drain region to the second underlying layer comprises a highly-doped region of the second conductivity type.

Claim 26

The MOS transistor of claim 22, wherein the first conductivity type comprises P-type.

Claim 27

The MOS transistor of claim 23, wherein the second conductivity type comprises N-type.

Claim 28

The MOS transistor of claim 22, wherein the first conductivity type comprises N-type.

Claim 29

The MOS transistor of claim 25, wherein the second conductivity type comprises P-type.

Claim 30

A lateral MOS transistor, comprising: a substrate including a first low-doped surface layer of a first conductivity type substantially coating a second more highly-doped underlying layer of the first conductivity type; a drain region of a second conductivity type formed in the first surface layer; a source region of the second conductivity type formed in the first surface layer; and a region of the second conductivity type extending through the surface layer from a portion of the drain region to the underlying layer.

Claim 31

A lateral MOS transistor, comprising: a substrate including a first low-doped surface layer of a first conductivity type substantially coating a second more highly-doped underlying layer of the first conductivity type; a drain region of a second conductivity type formed in the first surface layer; a source region of the second conductivity type formed in the first surface layer; and a region of the second conductivity type extending through the surface layer from a portion of the drain region to the underlying layer.

Claim 32

The MOS transistor of claim 27, further comprising a substrate contacting region formed in the first surface layer.

Claim 33

The MOS transistor of claim 28, wherein the source region, the drain region, and the substrate contacting region are formed in the first surface layer at a surface of the first surface layer.

Claim 34

The MOS transistor of claim 29, wherein the region of the second conductivity type extending through the first surface layer from a portion of the drain region to the second underlying layer comprises a highly-doped region of the second conductivity type.

Claim 35

The MOS transistor of claim 30, wherein the first conductivity type comprises P-type.

Claim 36

The MOS transistor of claim 31, wherein the second conductivity type comprises N-type.

Claim 37

The MOS transistor of claim 30, wherein the first conductivity type comprises N-type.

Claim 38

The MOS transistor of claim 33, wherein the second conductivity type comprises P-type.

Claim 39

The MOS transistor of claim 27, wherein the transistor is used as an output stage of a MOS type integrated circuit.

Claim 40

The MOS transistor of claim 27, wherein the transistor is constructed as an integrated circuit.

Claim 41

The MOS transistor of claim 28, wherein the substrate contacting region is interconnected to the source region.