Hetero-epitaxial growth of non-lattice matched semiconductors

Claim 2

A process for forming a layer of compound semiconductor material on a nonlattice matched substrate comprising the steps of forming a growth mask on a surface of the substrate, forming openings in the growth mask to expose areas of the substrate, forming an interlayer only on the exposed areas of the substrate by close-spaced-vapor-transport on the exposed areas in the openings of the growth mask, and forming the compound semiconductor layer over the interlayer by liquid phase epitaxy and using the interlayer in the exposed areas to seed the growth of the compound semiconductor layer.

Claim 3

The process of claim 1 wherein the interlayer is selected to enhance nucleation of the semi conductor material.

Claim 4

The process of claim 2 wherein the substrate is single crystal silicon and the compound semiconductor material is comprised of elements chosen from Groups III and V of the Periodic Table.

Claim 5

The process of claim 3 wherein the compound semiconductor material is GaAs and the interlayer is GaAs.

Claim 6

The process of claim 3 wherein the compound semiconductor is GaAs alloyed with AlAs in the amount of 20 mole per cent AlAs and the interlayer is GaAs.

Claim 7

The process of claim 3 wherein the compound semiconductor is InP and the interlayer is InP.

Claim 8

The process of claim 1 wherein the interlayer is GaAs and the close-spaced-vapor-transport step includes providing water vapor as a transporting agent.

Claim 9

The process of claim 1 wherein the interlayer is InP and the close-spaced-vapor-transport step includes providing hydrogen chloride as a transporting agent.

Claim 10

The process of claim 1 wherein the compound semiconductor is GaAs and the liquid phase epitaxy step includes providing a melt comprising a metal solvent comprising Bi.

Claim 11

The process of claim 1 wherein the compound semiconductor is InP and the liquid phase epitaxy step includes providing a melt comprising a solvent which is a mixture of Bi and In.

Claim 12

The process of claim 1 Wherein the compound semiconductor is InP and the liquid phase epitaxy step includes providing an InP cover to prevent loss of P.

Claim 13

The process of claim 1 wherein the compound semiconductor is InP and the liquid phase epitaxy step includes providing a source of P vapor species to prevent loss of P.

Claim 14

The process of claim 1 wherein the step of forming the interlayer includes doping the interlayer.

Claim 15

The process of claim 1 wherein the step of forming the compound semiconductor by liquid phase epitaxy includes providing dopants selected to obtain a desired conductivity type and concentration.

Claim 16

The process of claim 1 wherein the step of forming the compound semiconductor by liquid phase epitaxy includes step cooling to achieve a high degree of supersaturation.

Claim 17

The process of claim 1 where the step of providing a growth mask comprises growing a layer of silicon dioxide or silicon nitride over the substrate and forming an array of openings in said layer.

Claim 18

The process of claim 16 wherein the substrate is silicon and the step of providing the growth mask comprises growing a layer of silicon dioxide by thermal oxidation and forming an array of openings in the silicon dioxide by photolithography and chemical etching.

Claim 19

The process of claim 16 wherein the substrate is silicon and the step of providing the growth mask comprises selected area deposition by electron beam of silicon dioxide through an evaporation mask onto the substrate.

Claim 20

The process of claim 16 wherein the array of openings is a pattern comprising parallel stripes.

Claim 21

The process of claim 1 wherein the step of forming the compound semiconductor by liquid phase epitaxy includes lateral overgrowth of the semiconductor to form a continuous layer over the growth mask.

Claim 22

A process for fabricating a light emitting diode on a silicon substrate comprising the steps of: forming a silicon dioxide growth mask having an array of openings on the surface of the substrate; forming only on the exposed areas of substrate by close-spaced-vapor-transport growth on the exposed areas in openings in the growth mask an interlayer of a doped semiconductor material which functions as a base region of the light emitting diode and as a nucleation enhancing interlayer; and forming an emitter region of an oppositely doped compound semiconductor material over the interlayer by liquid phase epitaxy and using the interlayer in the exposed areas to seed the growth of the compound semiconductor material.

Claim 23

A process for fabricating a light emitting diode on a silicon substrate comprising the steps of: forming a silicon dioxide growth mask having an array of openings on the surface of the substrate; forming only on the exposed areas of substrate by close-spaced-vapor-transport growth on the exposed areas in openings in the growth mask an interlayer of a doped semiconductor material which functions as a base region of the light emitting diode and as a nucleation enhancing interlayer; and forming an emitter region of an oppositely doped compound semiconductor material over the interlayer by liquid phase epitaxy and using the interlayer in the exposed areas to seed the growth of the compound semiconductor material.

Claim 24

The process of claim 21 wherein the step of selectively forming the base region comprises close-spaced-vapor-transport growth of n-type GaAs using water vapor as a transporting agent and the step of forming the emitter region comprises liquid phase epitaxy growth of p-type AlGaAs containing 20 mole percent AlAs from a Bi solvent.

Claim 25

The process of claim 1 wherein close-spaced-vapor-transport includes providing a transport agent at a flow rate to remove oxides which form on the substrate.

Claim 26

The process of claim 1 wherein close-spaced-vapor-transport includes maintaining a sufficient temperature difference between a source and the substrate so that the interlayer only forms on the exposed areas of the substrate.

Claim 27

The process of claim 24 wherein the temperature difference between the source and the substrate is between 25 to 100° C.

Claim 28

The process of claim 1 wherein the liquid phase epitaxy step includes providing a melt comprising a metal solvent comprising Bi.