US5355336A — Memory device and a method for prohibiting writin…

Claim 1

Independent Claim 262 words

A memory device connected to a CPU and including a plurality of memory means selectable between a writable state and an unwritable state, the CPU outputting an address signal for selecting at least one of the plurality of memory means, data to be stored in the plurality of memory means, and a write signal for selecting one of the writable state and the unwritable state of the plurality of memory means to the memory device, the memory device comprising: address decoding means for generating at least two select signals in response to the address signal; first memory means for storing first data outputted from the CPU in response to a first state select signal having a specified level for selecting one of the writable state and the unwritable state when a first one of the two select signals is at a specified level; second memory means for storing and outputting second data outputted from the CPU in response to a second state select signal having a specified level for selecting one of the writable state and the unwritable state when a second one of the two select signals is at a specified level, the second data putting the first and the second memory means into the unwritable state; and logic operation means for performing logic operations of the write signal and the second data outputted from the second memory means and outputting signals indicating results of the logic operations to the first and the second memory means respectively, the signals indicating the results being the first and the second state select signals.

Claim 2

Dependent Claim 262 words

A memory device connected to a CPU and including a plurality of memory means selectable between a writable state and an unwritable state, the CPU outputting an address signal for selecting at least one of the plurality of memory means, data to be stored in the plurality of memory means, and a write signal for selecting one of the writable state and the unwritable state of the plurality of memory means to the memory device, the memory device comprising: address decoding means for generating at least two select signals in response to the address signal; first memory means for storing first data outputted from the CPU in response to a first state select signal having a specified level for selecting one of the writable state and the unwritable state when a first one of the two select signals is at a specified level; second memory means for storing and outputting second data outputted from the CPU in response to a second state select signal having a specified level for selecting one of the writable state and the unwritable state when a second one of the two select signals is at a specified level, the second data putting the first and the second memory means into the unwritable state; and logic operation means for performing logic operations of the write signal and the second data outputted from the second memory means and outputting signals indicating results of the logic operations to the first and the second memory means respectively, the signals indicating the results being the first and the second state select signals.

Claim 3

Dependent Claim 18 words

A memory device according to claim 1, wherein the logic operation means is a negative logic AND circuit.

Claim 4

Dependent Claim 45 words

A memory device according to claim 1, wherein initial data is set in the second memory means for putting the first memory means into the writable state before receiving the address signal, the first and the second data, and the write signal from the CPU.

Claim 5

Independent Claim 280 words

A method for prohibiting rewriting of data stored in a memory device connected to a CPU and including first and second memory means each selectable between a writable state and an unwritable state, the CPU outputting an address signal for selecting one of the plurality of memory means, data to be stored in the plurality of memory means, and a write signal for selecting one of the writable state and the unwritable state of the plurality of memory means to the memory device, the method comprising the steps of: setting initial data in the second memory means, the initial data having a specified level for putting the first memory means into the writable state before receiving the address signal, data to be stored, and the write signal from the CPU, and outputting the initial data from the second memory means; performing a first logic operation of the initial data and the write signal; outputting a state select signal indicating a result of the first logic operation for putting the second memory means into the writable state; writing first data to the first memory means when a first select signal is at a specified level; writing second data having a level inverse to the level of the initial data to the second memory means when a second select signal is at a specified level, and then outputting the second data; performing a second logic operation of the write signal and the second data; and outputting a writing prohibit signal indicating a result of the second logic operation and prohibiting writing to the first and the second memory means, thereby putting the first and the second memory means into the unwritable state.

Claim 6

Independent Claim 280 words

A method for prohibiting rewriting of data stored in a memory device connected to a CPU and including first and second memory means each selectable between a writable state and an unwritable state, the CPU outputting an address signal for selecting one of the plurality of memory means, data to be stored in the plurality of memory means, and a write signal for selecting one of the writable state and the unwritable state of the plurality of memory means to the memory device, the method comprising the steps of: setting initial data in the second memory means, the initial data having a specified level for putting the first memory means into the writable state before receiving the address signal, data to be stored, and the write signal from the CPU, and outputting the initial data from the second memory means; performing a first logic operation of the initial data and the write signal; outputting a state select signal indicating a result of the first logic operation for putting the second memory means into the writable state; writing first data to the first memory means when a first select signal is at a specified level; writing second data having a level inverse to the level of the initial data to the second memory means when a second select signal is at a specified level, and then outputting the second data; performing a second logic operation of the write signal and the second data; and outputting a writing prohibit signal indicating a result of the second logic operation and prohibiting writing to the first and the second memory means, thereby putting the first and the second memory means into the unwritable state.

Claim 7

Dependent Claim 102 words

A memory device, comprising: a memory array for storing data; a writing restriction register for prohibiting writing to the memory array as a function of data written to said writing restriction register and outputting a signal having a specified level as a result of said data being written to said writing restriction register; and logic operation means for receiving said signal output from said writing restriction register, for putting the writing restriction register into an unwritable state in response to said signal having said specified level outputted from the writing restriction register and for putting the memory array into the unrewritable state.

Claim 8

Dependent Claim 102 words

A memory device, comprising: a memory array for storing data; a writing restriction register for prohibiting writing to the memory array as a function of data written to said writing restriction register and outputting a signal having a specified level as a result of said data being written to said writing restriction register; and logic operation means for receiving said signal output from said writing restriction register, for putting the writing restriction register into an unwritable state in response to said signal having said specified level outputted from the writing restriction register and for putting the memory array into the unrewritable state.

Claim 9

Dependent Claim 16 words

A memory device according to claim 1, wherein said second memory means comprises a D-type flip-flop.

Claim 10

Dependent Claim 17 words

A memory device according to claim 1, wherein said second memory means comprises a non-volatile memory device.

Claim 11

Dependent Claim 82 words

A memory device, comprising: a first memory array and a second memory array; a first writing restriction register operative in combination with a first logic means for selectively prohibiting writing to said first memory means as a function of data written to said first writing restriction register; and a second writing restriction register operative in combination with a second logic means for selectively prohibiting writing to said second memory means as a function of data written to said second writing restriction register.

Claim 12

Dependent Claim 82 words

A memory device, comprising: a first memory array and a second memory array; a first writing restriction register operative in combination with a first logic means for selectively prohibiting writing to said first memory means as a function of data written to said first writing restriction register; and a second writing restriction register operative in combination with a second logic means for selectively prohibiting writing to said second memory means as a function of data written to said second writing restriction register.

Claim 13

Dependent Claim 25 words

A memory device according to claim 8, wherein at least one of said first and second writing restriction registers is always in a writable state.

Claim 14

Dependent Claim 48 words

A memory device according to claim 8, wherein at least one of said first and second writing restriction registers comprising means for selectively placing said at least one of said first and second writing restriction registers in an unwritable state as a function of said data written thereto.

Claim 15

Dependent Claim 46 words

A memory device according to claim 8, said first writing restriction register always being in a writable state, and said second writing restriction register comprising means for selectively placing said second writing restriction register in an unwritable state as a function of said data written thereto.

Claim 16

Dependent Claim 23 words

A memory device according to claim 8, wherein at least one of said first and second writing restriction registers comprises a D-type flip-flop.

Claim 17

Dependent Claim 23 words

A memory device according to claim 8, wherein at least one of said first and second writing restriction registers comprises a non-volatile memory.

Claim 18

Dependent Claim 35 words

A memory device according to claim 8, further comprising means for initializing said data written to at least one of said first and second writing restriction registers upon power being provided to said memory device.

Claim 19

Dependent Claim 19 words

A memory device according to claim 8, wherein said first and second memory arrays share a common data bus.

Claim 20

Dependent Claim 28 words

A memory device according to claim 8, wherein said first and second memory arrays and said first and second writing restriction registers all share a common data bus.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1997-10-10	1998-04-11	1998-10-11	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2001-10-10	2002-04-11	2002-10-11	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2005-10-10	2006-04-11	2006-10-11	$7700.00	Window Closed / Lapsed

Memory device and a method for prohibiting writing to the memory device

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