US5161122A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Register write bit protection apparatus and method
Assignee: Texas Instruments Inc
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Filing: 1989-07-28
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Granted: 1992-11-03
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Expires: 2009-07-28
Abstract
Abstract A register circuit and method which allows a multi-bit register to change states until such time as a particular dedicated bit is activated. Once the dedicated bit is turned to the logical on-state none of the bits, including the dedicated bit, can be changed until a reset signal is sensed.
Inventors
- 👤 Iain C. Robertson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:28
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1006; G11C7/20
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
141 words
A computer system, comprising: a first processor; and a second processor comprising: a central processing unit; a communications interface and an internal bus connecting the communications interface to said central processing unit, said communications interface connected for data transfer between said central processing unit and said first processor; at least one register including bit storage circuits connected to said internal bus; and a protection circuit connected to a control line from said internal bus to enable entry of data into said at least one register from said internal bus when the control line is active, and fed by at least one of said bit storage circuits having one of first and second sates, said protection circuit responsive to the first state to prevent entry of the data into any of said bit storage circuits even when the control line is active.
Claim 2
Dependent Claim
141 words
A computer system, comprising: a first processor; and a second processor comprising: a central processing unit; a communications interface and an internal bus connecting the communications interface to said central processing unit, said communications interface connected for data transfer between said central processing unit and said first processor; at least one register including bit storage circuits connected to said internal bus; and a protection circuit connected to a control line from said internal bus to enable entry of data into said at least one register from said internal bus when the control line is active, and fed by at least one of said bit storage circuits having one of first and second sates, said protection circuit responsive to the first state to prevent entry of the data into any of said bit storage circuits even when the control line is active.
Claim 3
Dependent Claim
34 words
The computer system of claim 1 wherein said protection circuit is responsive to said control line to enable entry of data into all of said bit storage circuits in said at least one register.
Claim 4
Dependent Claim
64 words
The computer system of claim 1 wherein only one of said bit storage circuits in said at least one register is dedicated to prevent entry, and said protection circuit includes a logic circuit responsive to a reset signal for resetting all of said bit storage circuits to a predetermined state even if an entry-preventing datum has been written to said dedicated bit storage circuit.
Claim 5
Dependent Claim
33 words
The computer system of claim 1 wherein said protection circuit includes a logic circuit responsive to a reset signal for resetting the state of each entry-preventing bit storage circuit to the second state.
Claim 6
Dependent Claim
21 words
The computer system of claim 1 wherein only one of said bit storage circuits feeds said protection circuit to prevent entry.
Claim 7
Dependent Claim
48 words
The computer system of claim 1 wherein said internal bus includes a read control line and said second processor further comprises an output enable circuit responsive to a read control line from said internal bus to supply data from said at least one register to said internal bus.
Claim 8
Dependent Claim
18 words
The computer system of claim 1 wherein said control line comprises a write line of said internal bus.
Claim 9
Dependent Claim
56 words
The computer system of claim 1 wherein a subset of said bit storage circuits are dedicated to prevent entry, and said central processing unit is operative to supply a write signal on the control line and to supply data to said at least one register including an entry preventing datum to each entry-preventing bit storage circuit.
Claim 10
Dependent Claim
126 words
A microprocessor device, comprising: a central processing unit; a communications interface and an internal bus connecting the communications interface to said central processing unit, said communications interface connected for data transfer externally; at least one register including bit storage circuits connected to said internal bus; and a protection circuit connected to a control line from said internal bus to enable entry of data into said at least one register from said internal bus when the control line is active, and fed by at least one of said bit storage circuits having one of a first and second state, said protection circuit responsive to the first state to prevent entry of the data into any of said bit storage circuits even when the control line is active.
Claim 11
Dependent Claim
126 words
A microprocessor device, comprising: a central processing unit; a communications interface and an internal bus connecting the communications interface to said central processing unit, said communications interface connected for data transfer externally; at least one register including bit storage circuits connected to said internal bus; and a protection circuit connected to a control line from said internal bus to enable entry of data into said at least one register from said internal bus when the control line is active, and fed by at least one of said bit storage circuits having one of a first and second state, said protection circuit responsive to the first state to prevent entry of the data into any of said bit storage circuits even when the control line is active.
Claim 12
Dependent Claim
101 words
A write protect circuit comprising: at least one register including bit storage circuits having inputs and outputs; gate logic having a control input to enable entry of data into all of the bit storage circuits of said at least one register when the control input is active; and protect logic, fed by at least one of said bit storage circuits having one of first and second states, said protect logic connected to said gate logic and responsive to the first state to prevent entry of the data into any of said bit storage circuits even when the control line is active.
Claim 13
Dependent Claim
101 words
A write protect circuit comprising: at least one register including bit storage circuits having inputs and outputs; gate logic having a control input to enable entry of data into all of the bit storage circuits of said at least one register when the control input is active; and protect logic, fed by at least one of said bit storage circuits having one of first and second states, said protect logic connected to said gate logic and responsive to the first state to prevent entry of the data into any of said bit storage circuits even when the control line is active.
Claim 14
Dependent Claim
30 words
The write protect circuit of claim 10 wherein said protect logic has a reset input and is responsive to a reset signal thereon to override response to said first state.
Claim 15
Independent Claim
92 words
A method of operating a computer having a central processing unit, a bus having data lines and at least one control line and at least one register including bit storage circuits connected to the bus, the method comprising the steps of: enabling entry of data into said at least one register from said bus when a control line is active and preventing entry of the data into any of said bit storage circuits, even when the control line is active, when a subset of the bit storage circuits has a predetermined state.
Claim 16
Independent Claim
92 words
A method of operating a computer having a central processing unit, a bus having data lines and at least one control line and at least one register including bit storage circuits connected to the bus, the method comprising the steps of: enabling entry of data into said at least one register from said bus when a control line is active and preventing entry of the data into any of said bit storage circuits, even when the control line is active, when a subset of the bit storage circuits has a predetermined state.
Claim 17
Dependent Claim
23 words
The method of claim 12 wherein said preventing step comprises loading said subset of said bit storage circuits to have said predetermined state.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-03 | 1996-05-04 | 1996-11-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-03 | 2000-05-04 | 2000-11-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-03 | 2004-05-04 | 2004-11-03 | $7700.00 | Window Closed / Lapsed |