Phase corrector for redundant clock systems and method

Claim 1

A redundant clock system for producing a pair of phase synchronized, master, clock output signals in response to a pair of asynchronous master clocks comprising: a pair of substantially identical phase corrector circuits for respectively producing on clock outputs thereof the pair of delay compensated, phase synchronized, master, clock output signals, each of said phase corrector circuits having a pair of inputs, one of said pair of inputs connected to a respective one of the pair of master clocks to receive an asynchronous master clock signal therefrom and another one of said pair of inputs connected to receive the delay compensated, phase synchronized, clock output signal from the other phase corrector, means for producing on the clock output a phase synchronized, master, clock output signal based on a selected one of said asynchronous master clock signal and said delay compensated output signal at said pair of inputs, means for selecting one of said master clock signal and said delay compensated output signal producing means, said selecting means introducing a propagation delay between the pair of inputs and the master clock output signal producing means, and means connected between the producing means and the output of the phase corrector circuit, for causing the delay compensated, phase synchronized, clock output signal to be provided with an amount of propagation delay to compensate for the propagation delay introduced by the selecting means for producing a phase synchronized, master clock output signal in phase with the selected one of said master clock signal and said delay compensated, phase synchronized, clock output signal; and means for controlling both of the phase corrector circuits to selectively produce synchronous master clock output signals in response to different ones of the pair of inputs at each of the phase correctors.