Clock pulse signal generator system

Claim 1

Apparatus for generating a stable clock pulse signal, said apparatus comprising in combination: (a) a first clock generator including: (1) a first output terminal adapted to present a first clock pulse signal; (2) first controllable oscillator means connected to said first output terminal for producing said first clock pulse signal, said first oscillator means having a first control input and being responsive to a first control signal applied to said first control input to vary the frequency of said first clock pulse signal; and (3) first control means connected to said first control input for producing said first control signal to maintain the frequency of said first clock pulse signal substantially constant; and (b) a second clock generator including: (1) a second output terminal adapted to present a second clock pulse signal; (2) a second input terminal connected to said first output terminal of said first clock generator and adapted to receive said first clock pulse signal from said first clock generator; (3) second controllable oscillator means connected to said second output terminal for producing said second clock pulse signal, said second oscillator means having a second control input and being responsive to a second control signal applied to said second control input to vary the frequency of said second clock pulse signal; and (4) second control means connected to said second input terminal and to said second control input for producing said second control signal in response to said first clock pulse signal, said second control signal causing the frequency and phase of said second clock pulse signal to closely follow the frequency and phase of said first clock pulse signal, the first and second control means each comprising a fine phase lead-lag counter and a fine phase latch connected to an output of the counter, the counter being enabled by an output of an emitter coupled logic gate, the emitter coupled logic gate output indicating a leading or lagging phase condition between the first and second clock pulse signal outputs of the first and second clock generators; (c) an external reference clock generator means for providing at least one reference clock signal through a reference clock interface to the first and second clock generators, one of the first clock generator or the second clock generator providing the stable clock pulse signal; and (d) a processing means, connected to the first and second control means, for processing data in accordance with a particular algorithm.

Claim 21

The apparatus defined in either one of claims 10 or 14, wherein said digital phase comparator means includes a digital, coarse phase counter, having a clock input connected to the respective output terminal of the clock generator in which it is disposed, for continuously counting the pulses in said clock pulse signal received from said respective output terminal; and a digital, coarse phase latch, connected to said coarse phase counter, for periodically receiving and storing the instantaneous, digital count in said coarse phase counter in response to pulses of said reference clock signal.

Claim 34

The apparatus defined in any one of claims 30, 31, or 32 wherein said first and said second control means switch their master/slave relationship if said first reference clock signal is found to be unstable by the control means in the master mode but not by the control means in the slave mode.

Claim 35

The apparatus defined in any one of claims 30, 31, or 32, wherein the operation of said first and said second control means remains unchanged if said reference clock signal is found to be unstable by the control means in the slave mode but not by the control means in the master mode.

Claim 46

A system for generating a stable clock pulse signal, said system comprising in combination first and second clock generator apparatus, to which apparatus is provided a reference clock signal by an external reference clock generator, the first and second clock generator apparatus each comprising in addition to a coarse phase control loop, a fine phase control loop, comprising at least a fine phase lead-lag counting means and a fine phase latch, the fine phase control loop for providing the results of a fine phase comparison to a processing means for controlling an oscillating means shared by both the coarse and fine phase control loops, the fine phase lead-lag counting means and fine phase latch for performing the fine phase comparison of two reference clock signal outputs of the first and second clock generator apparatus, the fine phase lead-lag counting means being enabled by an output signal of an emitter coupled logic gate indicating a leading or lagging phase condition between the two reference clock signal outputs of the first and second clock generator apparatus.

Claim 47

A system for generating a stable clock pulse signal, said system comprising in combination first and second clock generator apparatus, to which apparatus is provided a reference clock signal by an external reference clock generator, the first and second clock generator apparatus each comprising in addition to a coarse phase control loop, a fine phase control loop, comprising at least a fine phase lead-lag counting means and a fine phase latch, the fine phase control loop for providing the results of a fine phase comparison to a processing means for controlling an oscillating means shared by both the coarse and fine phase control loops, the fine phase lead-lag counting means and fine phase latch for performing the fine phase comparison of two reference clock signal outputs of the first and second clock generator apparatus, the fine phase lead-lag counting means being enabled by an output signal of an emitter coupled logic gate indicating a leading or lagging phase condition between the two reference clock signal outputs of the first and second clock generator apparatus.