Semiconductor device

Claim 2

A semiconductor device, comprising: a semiconductor layer formed on an insulator layer; an isolation gate electrode formed in an isolation region surrounding an active region on said semiconductor layer with an insulating first gate dielectric thin film interposed therebetween; a transfer gate electrode formed in said active region on said semiconductor layer with a second gate dielectric thin film interposed therebetween and extending to cross over said isolation gate electrode; a first channel region of a first conductivity type formed in said semiconductor layer throughout the region under said transfer gate electrode; a second channel region of the first conductivity type formed in said semiconductor layer through the region under said isolation gate electrode; second conductivity type source/drain regions formed in said semiconductor layer at opposite portions thereof interposing said first channel region therebetween, wherein said first and second channel regions contact each other only at regions where said transfer gate electrode intersects said isolation gate electrode, a prescribed electric potential is applied to said isolation gate electrode so as to prevent the surface of said second channel region from being inverted to be of the second conductivity type, and said first gate dielectric thin film has a contact hole formed therein for electrically connecting said isolation gate electrode and said second channel region.

Claim 3

The semiconductor device according to claim 1, wherein a ground potential is applied to said first channel region so as to prevent the surface of said second channel region from being inverted to be of said second conductivity type.

Claim 4

The semiconductor device according to claim 1, wherein a predetermined bias voltage is applied to said first channel region so as to prevent the surface of said second channel region from being inverted to be of the second conductivity type.

Claim 5

The semiconductor device according to claim 1, wherein said first and second channel regions comprise a silicon layer doped with p type impurities; said transfer gate electrode and said isolation gate electrode are formed of polycrystalline silicon doped with n type impurities; and said source/drain regions are formed by doping n type impurities into said semiconductor layer.

Claim 6

The semiconductor device according to claim 4, wherein a ground potential is applied to said first channel region so as to prevent the surface of said second channel region from being inverted to be of an n conductivity type.

Claim 7

The semiconductor device according to claim 3, wherein a negative bias is applied to said first channel region so as to prevent the surface of said second region from being inverted to be of the n conductivity type.

Claim 8

The semiconductor device according to claim 4, wherein said first and second channel regions have a p type impurity concentration of 10 16 -10 17 /cm 3 ; and said source/drain regions have an n type impurity concentration of 10 19 -10 21 /cm 3 .

Claim 9

The semiconductor device according to claim 1, wherein the same material as that of said isolation gate electrode is filled in said isolation contact hole.

Claim 10

A semiconductor device, comprising: a semiconductor layer formed on an insulator layer; a transfer gate electrode formed on said semiconductor layer with a gate dielectric thin film interposed therebetween; an isolation gate electrode formed on said semiconductor layer with a dielectric thin film for isolation interposed therebetween; a first channel region of a first conductivity type formed in said semiconductor layer below said transfer gate electrode; a second channel region of the first conductivity type formed in said semiconductor layer below said isolation gate electrode; second conductivity type source/drain regions formed in said semiconductor layer at opposite positions interposing said channel region below said transfer gate electrode therebetween; and a first conductivity type body region formed in said semiconductor layer below said isolation gate electrode and adjacent to said second channel region below said isolation gate electrode, wherein said body region has a body interconnection layer formed thereon, said body region and said body interconnection layer contact each other at a body contact disposed at the surface of said body region, and said body region and said body interconnection layer are isolated from said isolation gate electrode by an insulation layer interposed therebetween.

Claim 11

A semiconductor device, comprising: a semiconductor layer formed on an insulator layer; a transfer gate electrode formed on said semiconductor layer with a gate dielectric thin film interposed therebetween; an isolation gate electrode formed on said semiconductor layer with a dielectric thin film for isolation interposed therebetween; a first channel region of a first conductivity type formed in said semiconductor layer below said transfer gate electrode; a second channel region of the first conductivity type formed in said semiconductor layer below said isolation gate electrode; second conductivity type source/drain regions formed in said semiconductor layer at opposite positions interposing said channel region below said transfer gate electrode therebetween; and a first conductivity type body region formed in said semiconductor layer below said isolation gate electrode and adjacent to said second channel region below said isolation gate electrode, wherein said body region has a body interconnection layer formed thereon, said body region and said body interconnection layer contact each other at a body contact disposed at the surface of said body region, and said body region and said body interconnection layer are isolated from said isolation gate electrode by an insulation layer interposed therebetween.

Claim 12

The semiconductor device according to claim 9, wherein a ground potential is applied through said body contact and said body interconnection layer to said body region.

Claim 13

The semiconductor device according to claim 9, wherein said semiconductor layer comprises a silicon layer doped with p type impurities; said transfer gate electrode and said isolation gate electrode are formed of polycrystalline silicon doped with n type impurities; said source/drain regions are formed by doping n type impurities into said semiconductor layer; and said body region is formed by further doping p type impurities into said semiconductor layer.

Claim 14

The semiconductor device according to claim 11, wherein a ground potential is applied through said body contact and said body interconnection layer to said body region.

Claim 15

The semiconductor device according to claim 11, wherein said semiconductor layer has a p type impurity concentration of 10 16 -10 17 /cm 3 ; said source/drain regions have an n type impurity concentration of 10 19 -10 21 /cm 3 ; and said body region has a p type impurity concentration of 10 18 -10 20 /cm 3 .

Claim 16

The semiconductor device according to claim 9, wherein said first and second channel regions are electrically connected with each other.

Claim 17

A semiconductor device, comprising: an insulator layer; a semiconductor layer formed on said insulator layer, said semiconductor layer including a central active region circumscribed by an isolation region; a first dielectric thin film formed circumscribing said central active region on an upper surface of said isolation region; an isolation gate electrode formed circumscribing said active region on said first dielectric thin film; an elongate second dielectric thin film formed on an upper surface of said central active region, opposite ends of said elongate second dielectric thin film extending onto upper surfaces of said isolation gate electrode at opposing sides of said isolation region; an elongate transfer gate electrode formed on said elongate second dielectric thin film, opposite ends of said elongate transfer gate crossing over said upper surfaces of said isolating gate electrode at opposing sides of said isolation region; a first channel region of a first conductivity type formed in said semiconductor layer throughout the region under said transfer gate electrode; a second channel region of said first conductivity type formed in said semiconductor layer through the region under said isolation gate electrode; source/drain regions of a second conductivity type formed in said semiconductor layer on opposite sides of said first channel region, wherein said first and second channel regions contact each other only at regions whereat said transfer gate electrode crosses over said isolation gate electrode, a predetermined potential is applied to said isolation gate electrode so as to prevent the surface of said second channel region from being inverted to be of the second conductivity type, and said first dielectric thin film for isolation has a contact hole formed therein through which said gate electrode is electrically connected to said second channel region.

Claim 18

A semiconductor device, comprising: an insulator layer; a semiconductor layer formed on said insulator layer, said semiconductor layer including a central active region circumscribed by an isolation region; a first dielectric thin film formed circumscribing said central active region on an upper surface of said isolation region; an isolation gate electrode formed circumscribing said active region on said first dielectric thin film; an elongate second dielectric thin film formed on an upper surface of said central active region, opposite ends of said elongate second dielectric thin film extending onto upper surfaces of said isolation gate electrode at opposing sides of said isolation region; an elongate transfer gate electrode formed on said elongate second dielectric thin film, opposite ends of said elongate transfer gate crossing over said upper surfaces of said isolating gate electrode at opposing sides of said isolation region; a first channel region of a first conductivity type formed in said semiconductor layer throughout the region under said transfer gate electrode; a second channel region of said first conductivity type formed in said semiconductor layer through the region under said isolation gate electrode; source/drain regions of a second conductivity type formed in said semiconductor layer on opposite sides of said first channel region, wherein said first and second channel regions contact each other only at regions whereat said transfer gate electrode crosses over said isolation gate electrode, a predetermined potential is applied to said isolation gate electrode so as to prevent the surface of said second channel region from being inverted to be of the second conductivity type, and said first dielectric thin film for isolation has a contact hole formed therein through which said gate electrode is electrically connected to said second channel region.

Claim 19

The semiconductor device according to claim 15, further comprising a source of a ground potential applied to said first channel region so as to prevent a polarity inversion at the surface of said second channel region.

Claim 20

The semiconductor device according to claim 15, further comprising a source of a predetermined bias voltage applied to said first channel region so as to prevent the surface of second channel region from being inverted to be of the second conductivity type.

Claim 21

The semiconductor device according to claim 15, wherein said first and second channel regions each comprise a silicon layer doped with p type impurities; said transfer gate electrode and said isolation gate electrode are formed of polycrystalline silicon doped with n type impurities; and said source/drain regions are formed by doping n type impurities into said semiconductor layer.

Claim 22

The semiconductor device according to claim 18, wherein a ground potential is applied to said first channel region so as to prevent the surface of said second channel region from being inverted to be of an n conductivity type.

Claim 23

The semiconductor device according to claim 18, wherein said first and second channel regions have a p type impurity concentration of 10 16 -10 17 /cm 3 ; and said source/drain regions have an n type impurity concentration of 10 19 10 21 /cm 3 .

Claim 24

The semiconductor device according to claim 14, wherein said first and second channel regions contact with each other only at regions wherein said transfer gate electrode intersects said isolation gate electrode.