Thin-film soi mosfet and method of manufacturing thereof

Claim 1

An MOS field effect transistor comprising: an insulator substrate (2), a semiconductor layer (3) formed on said insulator substrate (2), a channel region (6) of a first conductivity type formed in said semiconductor layer (3), a source region (8) of a second conductivity type formed in said semiconductor layer (3) being in contact with one side of said channel region (6), a drain region (9) of the second conductivity type formed in said semiconductor layer (3) being in contact with the other side of said channel region (6), a body region (7) of the first conductivity type having a higher impurity concentration than that of said channel region (6) and being formed in contact with at least a part of said channel region (6) and at least a part of a periphery of said source region (8) in said semiconductor layer (3), a gate dielectric thin film (4) formed on said channel region (6), a gate electrode (5) formed on said dielectric thin film (4), a first conductor (14a) connected in common to said source region (8) and said body region (7), a second conductor (14b) connected to said gate electrode (5), a third conductor (14c) connected to said drain region (9).

Claim 8

A method of manufacturing an MOS field effect transistor comprising the steps of: forming a silicon layer (3) of a first conductivity type on an insulator substrate (2), covering said silicon layer (3) with a nitride layer (16), covering a part of said nitride layer (16) with a first resist layer (17), etching said nitride layer (16) using said first resist layer (17) as a mask, thereby leaving said nitride layer (16) on a transistor region of said silicon layer (3), forming a body region (7) in an outer periphery of the transistor region of said silicon layer (3) by implanting ions of an impurity (18) of the first conductivity type using said resist layer (17) as a mask, forming an isolation oxide film (10) and diffusing the impurity in said body region (7) toward inside of said transistor region by thermally oxidizing said silicon layer (3) using said nitride layer (16) as a mask after the removal of said first resist layer (17), thereby leaving the body region (7) at least under a bird's beak of said isolation oxide film (10) in a peripheral portion of said transistor region of said silicon layer (3), forming a gate insulating film (4) and a gate electrode (5) using a second resist layer (20) after the removal of said nitride film (16), forming a source region (8) and a drain region (9) by implanting ions of an impurity (19) of a second conductivity type using said second resist layer (20) and said isolation oxide film (10) as masks, covering said silicon layer (3) and said gate electrode (5) with an interlayer insulating film (11) after the removal of said second resist layer (20), forming a contact hole (12a) exposing not only a part of said source region (8) but also a part of said body region (7), forming a conductor (14a) to be connected to said source region (8) and said body region (7) through said contact hole (12a).

Claim 9

A method of manufacturing an MOS field effect transistor comprising the steps of: forming a silicon layer (3) of a first conductivity type on an insulator substrate (2), covering said silicon layer (3) with a nitride layer (16), covering a part of said nitride layer (16) with a first resist layer (17), etching said nitride layer (16) using said first resist layer (17) as a mask, thereby leaving said nitride layer (16) on a transistor region of said silicon layer (3), forming a body region (7) in an outer periphery of the transistor region of said silicon layer (3) by implanting ions of an impurity (18) of the first conductivity type using said resist layer (17) as a mask, forming an isolation oxide film (10) and diffusing the impurity in said body region (7) toward inside of said transistor region by thermally oxidizing said silicon layer (3) using said nitride layer (16) as a mask after the removal of said first resist layer (17), thereby leaving the body region (7) at least under a bird's beak of said isolation oxide film (10) in a peripheral portion of said transistor region of said silicon layer (3), forming a gate insulating film (4) and a gate electrode (5) using a second resist layer (20) after the removal of said nitride film (16), forming a source region (8) and a drain region (9) by implanting ions of an impurity (19) of a second conductivity type using said second resist layer (20) and said isolation oxide film (10) as masks, covering said silicon layer (3) and said gate electrode (5) with an interlayer insulating film (11) after the removal of said second resist layer (20), forming a contact hole (12a) exposing not only a part of said source region (8) but also a part of said body region (7), forming a conductor (14a) to be connected to said source region (8) and said body region (7) through said contact hole (12a).

Claim 11

A method of manufacturing an MOS field effect transistor comprising the steps of: forming a semiconductor layer (3) of a first conductivity type on an insulator substrate (2), covering said semiconductor layer (3) with an oxide layer (22), covering a part of said oxide layer (22) with a first resist layer, etching said oxide layer (22) using said first resist layer as a mask, thereby leaving said oxide layer (22) on a transistor region of said semiconductor layer (3), forming a body region (7) in an outer periphery of the transistor region of said semiconductor layer (3) by implanting ions of an impurity of the first conductivity type using said first resist layer as a mask, diffusing the impurity in said body region (7) toward inside of said transistor region by a heat treatment in an inert atmosphere after the removal of said first resist layer, so that said body region (7) extends under a peripheral portion of said oxide layer (22), leaving the transistor region of said semiconductor layer (3) as an island by etching using, said oxide layer (22) as a mask, forming a gate insulating film (4) and a gate electrode (5) using a second resist layer after the removal of said oxide layer (22), forming a source region (8) and a drain region (9) by implanting ions of an impurity of a second conductivity type using in addition to said second resist layer, a third resist layer covering said body region (7) as a mask, covering said semiconductor layer (3) and said gate electrode (5) with an interlayer insulating film (11) after the removal of said second and third resist layers, forming a contact hole (12a) exposing not only a part of said source region (8) but also a part of said body region (7), forming a conductor (14a) to be connected to said source region (8) and said body region (7) through said contact hole (12a).

Claim 12

A method of manufacturing an MOS field effect transistor comprising the steps of: forming a semiconductor layer (3) of a first conductivity type on an insulator substrate (2), covering said semiconductor layer (3) with an oxide layer (22), covering a part of said oxide layer (22) with a first resist layer, etching said oxide layer (22) using said first resist layer as a mask, thereby leaving said oxide layer (22) on a transistor region of said semiconductor layer (3), forming a body region (7) in an outer periphery of the transistor region of said semiconductor layer (3) by implanting ions of an impurity of the first conductivity type using said first resist layer as a mask, diffusing the impurity in said body region (7) toward inside of said transistor region by a heat treatment in an inert atmosphere after the removal of said first resist layer, so that said body region (7) extends under a peripheral portion of said oxide layer (22), leaving the transistor region of said semiconductor layer (3) as an island by etching using, said oxide layer (22) as a mask, forming a gate insulating film (4) and a gate electrode (5) using a second resist layer after the removal of said oxide layer (22), forming a source region (8) and a drain region (9) by implanting ions of an impurity of a second conductivity type using in addition to said second resist layer, a third resist layer covering said body region (7) as a mask, covering said semiconductor layer (3) and said gate electrode (5) with an interlayer insulating film (11) after the removal of said second and third resist layers, forming a contact hole (12a) exposing not only a part of said source region (8) but also a part of said body region (7), forming a conductor (14a) to be connected to said source region (8) and said body region (7) through said contact hole (12a).

Claim 13

A method of manufacturing an MOS field effect transistor comprising the steps of: forming a silicon layer (3) of a first conductivity type on an insulator substrate (2), covering said silicon layer (3) with a nitride layer (16), covering a part of said nitride layer (16) with a first resist layer (17), etching said nitride layer (16) using said first said resist layer (17) as a mask, thereby leaving said nitride layer (16) on a transistor region of said silicon layer (3), forming a body region (7) in an outer periphery of the transistor region of said silicon layer (3) by implanting ions of an impurity (18) of the first conductivity type using said first resist layer (17) as a mask, forming an isolation oxide film (10) and diffusing the impurity in said body region (7) toward inside of said transistor region by thermally oxidizing said silicon layer (3) using said nitride layer (16) as a mask after the removal of said first resist layer (17), thereby leaving the body region (7) at least under a bird's beak of said isolation oxide film (10) in a peripheral portion of said transistor region of said silicon layer (3), implanting ions of an impurity (25) of the first conductivity type in a lower partial layer (7a) of a first region, using a second resist layer (24a) covering a second region in said transistor region as a mask, forming a gate insulating film (4) and a gate electrode (5) along a boundary between said first and second regions, using a third resist layer (20) after the removal of said second resist layer (24a), forming a source region (8) and a drain region (9), and leaving an additional body region (7a) extending in contact with said source region (8) in a lower partial layer in a channel region (6) provided between said source region (8) and said drain region (9), by implanting ions of an impurity (19) of a second conductivity type, using said third resist layer (20) and said isolation oxide film (10) as masks, covering said silicon layer (3) and said gate electrode (5) with an interlayer insulating film (11) after the removal of said third resist layer, forming a contact hole (12a) exposing not only a part of said source region (8) but also a part of said body region (7), forming a conductor (14a) to be connected to said source region (8) and body region (7) through said contact hole (12a).

Claim 14

A method of manufacturing an MOS field effect transistor comprising the steps of: forming a silicon layer (3) of a first conductivity type on an insulator substrate (2), covering said silicon layer (3) with a nitride layer (16), covering a part of said nitride layer (16) with a first resist layer (17), etching said nitride layer (16) using said first said resist layer (17) as a mask, thereby leaving said nitride layer (16) on a transistor region of said silicon layer (3), forming a body region (7) in an outer periphery of the transistor region of said silicon layer (3) by implanting ions of an impurity (18) of the first conductivity type using said first resist layer (17) as a mask, forming an isolation oxide film (10) and diffusing the impurity in said body region (7) toward inside of said transistor region by thermally oxidizing said silicon layer (3) using said nitride layer (16) as a mask after the removal of said first resist layer (17), thereby leaving the body region (7) at least under a bird's beak of said isolation oxide film (10) in a peripheral portion of said transistor region of said silicon layer (3), implanting ions of an impurity (25) of the first conductivity type in a lower partial layer (7a) of a first region, using a second resist layer (24a) covering a second region in said transistor region as a mask, forming a gate insulating film (4) and a gate electrode (5) along a boundary between said first and second regions, using a third resist layer (20) after the removal of said second resist layer (24a), forming a source region (8) and a drain region (9), and leaving an additional body region (7a) extending in contact with said source region (8) in a lower partial layer in a channel region (6) provided between said source region (8) and said drain region (9), by implanting ions of an impurity (19) of a second conductivity type, using said third resist layer (20) and said isolation oxide film (10) as masks, covering said silicon layer (3) and said gate electrode (5) with an interlayer insulating film (11) after the removal of said third resist layer, forming a contact hole (12a) exposing not only a part of said source region (8) but also a part of said body region (7), forming a conductor (14a) to be connected to said source region (8) and body region (7) through said contact hole (12a).

Claim 16

A method of manufacturing an MOS field effect transistor comprising the steps of: forming a p type silicon layer (3) on an insulator substrate (2), covering said silicon layer (3) with a nitride layer (10), covering a part of said nitride layer (16) with a first resist layer (17), etching said nitride layer (16) using said first resist layer (17) as a mask, thereby leaving said nitride layer (16) on a transistor region of said silicon layer (3), forming a body region (7) in an outer periphery of the transistor region of said silicon layer (3) by implanting ions of a p type impurity (18) using said first resist layer (17) as a mask, forming an isolation oxide film (10) and diffusing the impurity in said body region (7) toward inside of said transistor region by thermally oxidizing said silicon layer (3), using said nitride layer (16) as a mask, after the removal of said first resist layer (17), thereby leaving the body region (7) at least under a bird's beak of said isolation oxide film (10) in a peripheral portion of said transistor region of said silicon layer (3), forming a gate insulating film (4) and a gate electrode (5) using a second resist layer (20) after the removal of said nitride layer (16), forming a source region (8) and a drain region (9) by implanting ions of an n type impurity (19), using said second resist layer (20) and said isolation oxide film (10) as masks, implanting ions of a p type impurity in a lower partial layer of said source region (8), using a third resist layer (24b) covering said drain region (9), diffusing the p type impurity of the lower partial layer of said source region (8) into said channel region (6) by heat treatment in an inert atmosphere after the removal of said second and third resist layers (21, 24b), thereby forming an additional body region (7a) extending in contact with said source region (8) in a lower partial layer of said channel region (6), covering said silicon layer (3) and said gate electrode (5) with an interlayer insulating film (11), forming a contact hole (12a) exposing not only a part of said source region (8) but also a part of said body region (7), forming a conductor (14a) to be connected to said source region (8) and body region (7) through said contact hole (12a).

Claim 17

A method of manufacturing an MOS field effect transistor comprising the steps of: forming a p type silicon layer (3) on an insulator substrate (2), covering said silicon layer (3) with a nitride layer (10), covering a part of said nitride layer (16) with a first resist layer (17), etching said nitride layer (16) using said first resist layer (17) as a mask, thereby leaving said nitride layer (16) on a transistor region of said silicon layer (3), forming a body region (7) in an outer periphery of the transistor region of said silicon layer (3) by implanting ions of a p type impurity (18) using said first resist layer (17) as a mask, forming an isolation oxide film (10) and diffusing the impurity in said body region (7) toward inside of said transistor region by thermally oxidizing said silicon layer (3), using said nitride layer (16) as a mask, after the removal of said first resist layer (17), thereby leaving the body region (7) at least under a bird's beak of said isolation oxide film (10) in a peripheral portion of said transistor region of said silicon layer (3), forming a gate insulating film (4) and a gate electrode (5) using a second resist layer (20) after the removal of said nitride layer (16), forming a source region (8) and a drain region (9) by implanting ions of an n type impurity (19), using said second resist layer (20) and said isolation oxide film (10) as masks, implanting ions of a p type impurity in a lower partial layer of said source region (8), using a third resist layer (24b) covering said drain region (9), diffusing the p type impurity of the lower partial layer of said source region (8) into said channel region (6) by heat treatment in an inert atmosphere after the removal of said second and third resist layers (21, 24b), thereby forming an additional body region (7a) extending in contact with said source region (8) in a lower partial layer of said channel region (6), covering said silicon layer (3) and said gate electrode (5) with an interlayer insulating film (11), forming a contact hole (12a) exposing not only a part of said source region (8) but also a part of said body region (7), forming a conductor (14a) to be connected to said source region (8) and body region (7) through said contact hole (12a).

Claim 19

A method of manufacturing an MOS field effect transistor comprising the steps of: forming a silicon layer (3) of a first conductivity type on an insulator substrate (2), covering said silicon layer (3) with a nitride layer (16), covering a part of said nitride layer (16) with a first resist layer (17), etching said nitride layer (16) using said first resist layer (17) as a mask, thereby leaving said nitride layer (16) on a transistor region of said silicon layer (3), forming body region (7) in an outer periphery of the transistor region of said silicon layer (3) by implanting ions of an impurity (18) of the first conductivity type using said first resist layer (17) as a mask, forming an isolation oxide film (10) by thermally oxidizing said silicon layer (3) using said nitride layer (16) as a mask after the removal of said first resist layer (17) and diffusing the impurity in said body region (7) toward inside of said transistor region, thereby leaving the body region (7) at least under a bird's beak of said isolation oxide film (10) in a peripheral portion of said transistor region of said silicon layer (3), forming a gate insulating film (4) and a gate electrode (5) using a second resist layer (20) after the removal of said nitride layer (16), implanting ions of an impurity (25a) of a second conductivity type in a lower partial layer (7a) of said source region (8), using a third resist layer (24c) covering said drain region (9), forming a source layer (8a) and a drain layer (9a) of low impurity concentration by implanting ions of an impurity (19a) of the second conductivity type into an upper portion layer portion of said silicon layer (3) after the removal of said second and third resist layers (20, 24c), forming an oxide layer (50) on a side wall of said gate electrode (5) by isotopic etching, forming a source region (8) and a drain region (9) by implanting ions of an impurity (19b) of the second conductivity type into said silicon layer (3), thereby leaving an additional body region (7a) in a lower partial layer portion between the source region (8) and the channel region (6), and leaving a lightly doped drain region (9a) in contact with the drain region (8), covering said semiconductor layer (3) and said gate electrode (5) with an interlayer insulating film (11), forming a contact hole (12a) exposing not only a part of said source region (8) but also a part of said body region (7), forming a conductor (14a) to be connected with said source region (8) and body region (7) through said contact hole (12a).

Claim 20

A method of manufacturing an MOS field effect transistor comprising the steps of: forming a silicon layer (3) of a first conductivity type on an insulator substrate (2), covering said silicon layer (3) with a nitride layer (16), covering a part of said nitride layer (16) with a first resist layer (17), etching said nitride layer (16) using said first resist layer (17) as a mask, thereby leaving said nitride layer (16) on a transistor region of said silicon layer (3), forming body region (7) in an outer periphery of the transistor region of said silicon layer (3) by implanting ions of an impurity (18) of the first conductivity type using said first resist layer (17) as a mask, forming an isolation oxide film (10) by thermally oxidizing said silicon layer (3) using said nitride layer (16) as a mask after the removal of said first resist layer (17) and diffusing the impurity in said body region (7) toward inside of said transistor region, thereby leaving the body region (7) at least under a bird's beak of said isolation oxide film (10) in a peripheral portion of said transistor region of said silicon layer (3), forming a gate insulating film (4) and a gate electrode (5) using a second resist layer (20) after the removal of said nitride layer (16), implanting ions of an impurity (25a) of a second conductivity type in a lower partial layer (7a) of said source region (8), using a third resist layer (24c) covering said drain region (9), forming a source layer (8a) and a drain layer (9a) of low impurity concentration by implanting ions of an impurity (19a) of the second conductivity type into an upper portion layer portion of said silicon layer (3) after the removal of said second and third resist layers (20, 24c), forming an oxide layer (50) on a side wall of said gate electrode (5) by isotopic etching, forming a source region (8) and a drain region (9) by implanting ions of an impurity (19b) of the second conductivity type into said silicon layer (3), thereby leaving an additional body region (7a) in a lower partial layer portion between the source region (8) and the channel region (6), and leaving a lightly doped drain region (9a) in contact with the drain region (8), covering said semiconductor layer (3) and said gate electrode (5) with an interlayer insulating film (11), forming a contact hole (12a) exposing not only a part of said source region (8) but also a part of said body region (7), forming a conductor (14a) to be connected with said source region (8) and body region (7) through said contact hole (12a).