Semiconductor IC device with improved element isolating scheme

Claim 2

A semiconductor IC device characterized in that in an element isolating region for electrically isolating semiconductor elements from each other, said device comprises a semiconductor substrate (1) of a first conductive type, a first insulative layer (2) formed on said semiconductor substrate (1), a conductive layer (3) formed on said first insulative layer (2) in an element isolating region and applied with a constant potential, a second insulative layer (4) formed on a surface of said conductive layer (3), and impurity regions (6, 7) of a second conductive type formed in a surface region of said semiconductor substrate (1) on both sides of said conductive layer (3); and that a normally-OFF MOS transistor (Q2) formed with said conductive layer (3) serving as a gate electrode, said first insulative layer (2) serving as a gate insu­lative film and said impurity regions (6, 7) serving as source and drain regions, is used as an element isolat­ing region.

Claim 3

A device according to claim 1, characterized in that said device further comprises a second con­ductive layer (5) formed on said second insulative layer (4) and said first insulative layer (2), and an MOS transistor (Q1) is formed with said second conductive layer (5) serving as a gate electrode, said first insu­lative layer (2) serving as a gate insulative film and said impurity regions (6, 7) serving as source and drain regions.

Claim 4

A device according to claim 1, characterized in that said conductive layer (3) includes a poly­crystalline silicon layer and said second insulative layer (4) includes a silicon oxide film formed by oxidi­zation of a surface of said polycrystalline silicon layer.

Claim 5

A semiconductor IC device characterized in that in an element isolating region for electrically isolating semiconductor elements from each other, said device comprises a semiconductor substrate (1) of a first conductive type, a first oxide film (2) formed on said semiconductor substrate (1), a first polycrys­talline silicon layer (3) formed on said first oxide film (2) in an element isolating region and applied with a constant potential, a second oxide film (4) formed on a surface of said first polycrystalline silicon layer (3), a second polycrystalline silicon layer (5) formed on part of said second oxide film (4) and part of said first oxide film (2), first impurity regions (6, 7) of a second conductive type formed in a surface region of said semiconductor substrate (1) on both sides of said second polycrystalline silicon layer (5), a first MOS transistor (Q1) being formed with said first impurity regions (6, 7) serving as source and drain regions, said first oxide film (2) serving as a gate insulative film and said second polycrystalline silicon layer (5) serv­ing as a gate electrode, a third polycrystalline silicon layer formed on part of said second oxide film (4) and part of said first oxide film (2) and isolated from said second polycrystalline silicon layer (5), and second impurity regions (6, 7) of said second conductive type formed in a surface region of said semiconductor sub­strate (1) on both sides of said third polycrystalline silicon layer, a second MOS transistor being formed with said second impurity regions (6, 7) serving as source and drain regions, said first oxide film (2) serving as a gate insulative film and said third polycrystalline silicon layer serving as a gate electrode; and that a normally-OFF parasitic MOS transistor (Q2) formed with said first polycrystalline silicon layer (3) serving as a gate electrode, said first oxide film (2) serving as a gate insulative film and one of said first impurity regions (6, 7) and one of said second impurity regions (6, 7) respectively serving as source and drain regions, is used as an element isolating region to sepa­rate said first MOS transistor (Q1) from said second MOS transistor.

Claim 6

A semiconductor IC device characterized in that in an element isolating region for electrically isolating semiconductor elements from each other, said device comprises a semiconductor substrate (1) of a first conductive type, a first oxide film (2) formed on said semiconductor substrate (1), a first polycrys­talline silicon layer (3) formed on said first oxide film (2) in an element isolating region and applied with a constant potential, a second oxide film (4) formed on a surface of said first polycrystalline silicon layer (3), a second polycrystalline silicon layer (5) formed on part of said second oxide film (4) and part of said first oxide film (2), first impurity regions (6, 7) of a second conductive type formed in a surface region of said semiconductor substrate (1) on both sides of said second polycrystalline silicon layer (5), a first MOS transistor (Q1) being formed with said first impurity regions (6, 7) serving as source and drain regions, said first oxide film (2) serving as a gate insulative film and said second polycrystalline silicon layer (5) serv­ing as a gate electrode, a third polycrystalline silicon layer formed on part of said second oxide film (4) and part of said first oxide film (2) and isolated from said second polycrystalline silicon layer (5), and second impurity regions (6, 7) of said second conductive type formed in a surface region of said semiconductor sub­strate (1) on both sides of said third polycrystalline silicon layer, a second MOS transistor being formed with said second impurity regions (6, 7) serving as source and drain regions, said first oxide film (2) serving as a gate insulative film and said third polycrystalline silicon layer serving as a gate electrode; and that a normally-OFF parasitic MOS transistor (Q2) formed with said first polycrystalline silicon layer (3) serving as a gate electrode, said first oxide film (2) serving as a gate insulative film and one of said first impurity regions (6, 7) and one of said second impurity regions (6, 7) respectively serving as source and drain regions, is used as an element isolating region to sepa­rate said first MOS transistor (Q1) from said second MOS transistor.

Claim 7

A device according to claim 1 or 4, charac­terized in that said first conductivity type is P type and said second conductivity type is N type, and said constant potential is a ground potential.

Claim 8

A device according to claim 1 or 4, character­ized in that said first conductivity type is N type and said second conductivity type is P type, and said con­stant potential is a source potential (V DD ).

Claim 9

A device according to claim 4, character­ized in that said second oxide film (4) includes a silicon oxide film formed by oxidization of a surface of said first polycrystalline silicon layer (3).

Claim 10

A semiconductor IC device characterized in that in an element isolating region for electrically isolating semiconductor elements from each other, said device comprises a semiconductor substrate (11) of a first conductive type, a field oxide film (10) formed on a major surface of said semiconductor substrate (11), a first insulative layer (12) formed on said semiconductor substrate (11) isolated by said field oxide film (10), a conductive layer (13), formed on said field oxide film (10) at a boundary between said first insulative layer (12) and said field oxide film (10) and applied with a ground potential, a second insulative layer (14) formed on a surface of said conductive layer (13), and a semi­conductor element (Q3) formed in an element region (18) separated by said field oxide film 10) in said semi­conductor substrate (11); and that by preventing a bias voltage from being applied to said field oxide film (10) under said con­ductive layer (13) by means of said conductive layer (13), a parasitic field MOS transistor formed with said field oxide film (10) serving as a gate insulative film, a wiring layer formed on said field oxide film (10) serving as a gate electrode, and impurity regions (16, 17) of a second conductivity type formed in said semi­conductor substrate (11) as part of said semiconductor element (Q3) serving as source and drain regions, is prevented from becoming conductive.

Claim 11

A semiconductor IC device characterized in that in an element isolating region for electrically isolating semiconductor elements from each other, said device comprises a semiconductor substrate (11) of a first conductive type, a field oxide film (10) formed on a major surface of said semiconductor substrate (11), a first insulative layer (12) formed on said semiconductor substrate (11) isolated by said field oxide film (10), a conductive layer (13), formed on said field oxide film (10) at a boundary between said first insulative layer (12) and said field oxide film (10) and applied with a ground potential, a second insulative layer (14) formed on a surface of said conductive layer (13), and a semi­conductor element (Q3) formed in an element region (18) separated by said field oxide film 10) in said semi­conductor substrate (11); and that by preventing a bias voltage from being applied to said field oxide film (10) under said con­ductive layer (13) by means of said conductive layer (13), a parasitic field MOS transistor formed with said field oxide film (10) serving as a gate insulative film, a wiring layer formed on said field oxide film (10) serving as a gate electrode, and impurity regions (16, 17) of a second conductivity type formed in said semi­conductor substrate (11) as part of said semiconductor element (Q3) serving as source and drain regions, is prevented from becoming conductive.

Claim 12

A device according to claim 8, characterized in that said semiconductor element includes an MOS transis­tor (Q3).

Claim 13

A device according to claim 9, character­ized in that said MOS transistor (Q3) includes a poly­crystalline silicon layer (15) formed on part of said second insulative layer (14) and part of said first insulative layer (12), and first and second impurity regions (16, 17) formed in said semiconductor substrate (11) at both sides of said polycrystalline silicon layer (15) in said element region (18) separated by said field oxide film (10) and serving as source and drain regions.

Claim 14

A device according to claim 8, character­ized in that said second insulative layer (14) includes a silicon oxide film formed by oxidization of a surface of said conductive layer (13).

Claim 15

A semiconductor IC device characterized in that in an element isolating region for electrically isolating semiconductor elements from each other, said device comprises a semiconductor substrate (11) of a first conductive type, a field oxide film (10) formed on a major surface of said semiconductor substrate (11), a first oxide film (10) formed on said semiconductor substrate (11) isolated by said field oxide film (10), a first polycrystalline silicon layer (13), formed on said field oxide film (10) at a boundary between said first oxide film (12) and said field oxide film (10) and applied with a ground potential, a second oxide film (14) formed on a surface of said first polycrystalline silicon layer (13), a second polycrystalline silicon layer (15) formed on part of said second oxide film (14) and part of said first oxide film (12), and impurity regions (16, 17) of a second conductive type formed in a surface region of said semiconductor substrate (11) on both sides of said second polycrystalline silicon layer (15), an MOS transistor (Q3) being formed with said impurity regions (16, 17) serving as source and drain regions, said first oxide film (12) serving as a gate insulative film and said second polycrystalline silicon layer (15) serving as a gate electrode; and that by preventing a bias voltage from being applied to said field oxide film (10) under said first polycrystalline silicon layer (13) by means of said polycrystalline silicon layer (13), a parasitic field MOS transistor formed with said field oxide film (10) serving as a gate insulative film, a wiring layer formed on said field oxide film (10) serving as a gate elec­trode, and one of said impurity regions (16, 17) of said second conductivity type as said source and drain regions of said MOS transistor (Q3) and one of said impurity regions (16, 17) in another element region separated by said field oxide film (10) respectively serving as source and drain regions, is prevented from becoming conductive.

Claim 16

A semiconductor IC device characterized in that in an element isolating region for electrically isolating semiconductor elements from each other, said device comprises a semiconductor substrate (11) of a first conductive type, a field oxide film (10) formed on a major surface of said semiconductor substrate (11), a first oxide film (10) formed on said semiconductor substrate (11) isolated by said field oxide film (10), a first polycrystalline silicon layer (13), formed on said field oxide film (10) at a boundary between said first oxide film (12) and said field oxide film (10) and applied with a ground potential, a second oxide film (14) formed on a surface of said first polycrystalline silicon layer (13), a second polycrystalline silicon layer (15) formed on part of said second oxide film (14) and part of said first oxide film (12), and impurity regions (16, 17) of a second conductive type formed in a surface region of said semiconductor substrate (11) on both sides of said second polycrystalline silicon layer (15), an MOS transistor (Q3) being formed with said impurity regions (16, 17) serving as source and drain regions, said first oxide film (12) serving as a gate insulative film and said second polycrystalline silicon layer (15) serving as a gate electrode; and that by preventing a bias voltage from being applied to said field oxide film (10) under said first polycrystalline silicon layer (13) by means of said polycrystalline silicon layer (13), a parasitic field MOS transistor formed with said field oxide film (10) serving as a gate insulative film, a wiring layer formed on said field oxide film (10) serving as a gate elec­trode, and one of said impurity regions (16, 17) of said second conductivity type as said source and drain regions of said MOS transistor (Q3) and one of said impurity regions (16, 17) in another element region separated by said field oxide film (10) respectively serving as source and drain regions, is prevented from becoming conductive.

Claim 17

A device according to claim 8 or 12, charac­terized in that said first conductivity type is P type and said second conductivity type is N type.

Claim 18

A device according to claim 12, character­ized in that said second oxide film (14) includes a silicon oxide film formed by oxidization of a surface of said first polycrystalline silicon layer (13).