Information processing apparatus in which a cache memory can be operated in both store-in and store-through modes

Claim 2

An information processing apparatus comprising: (a) two or more processor units each including a cache memory and a processor which accesses stored data via the cache memory, and (b) a main storage coupled to said processor units; (c) each of said processor units including (i) a control status register for storing information about the processor's control status; (ii) discriminating means for discriminating, based on information in said control status register when data is loaded into the cache memory from said main storage, which one of store-through and store-in systems is to be used to write data in said cache memory, said discriminating means giving to the data an attribute indicating the store-through or the store-in system in accordance with the discriminating results by said discriminating means, and (iii) writing means for writing the loaded data in the cache memory using the discriminated one of said systems.

Claim 3

A cache memory control method for use in an information processing apparatus composed of a main storage, for storing a plurality of blocks of data, and a plurality of processor units, said processor units each including a processor having a control status register for storing information about the processor's control status, a private cache memory associated with said processor and said main storage, and a cache memory controller associated with said processor and said private cache memory, said method comprising the steps of: a) providing a read-request for reading a block of data from one of said processors to the cache memory controller associated therewith, said read-request including information indicating an address for designating a storage location of the main storage where the data to be read is stored; b) in the cache memory controller which has received said read-request from the associated processor, loading the block of data from a storage location of said main storage, designated by the address information included in said read-request, into a storage location of the associated private cache memory if said block of data is not already present in the private cache memory, discriminating, based on information in said control status register, whether the requested data is to be controlled using a store-in system or a store-through system, and storing a flag indicating the discriminated system in relation to the storage location of the associated private cache memory where said block of data was loaded; and c) updating a block of data stored in said main storage with a corresponding block of data stored in the private cache memory associated with said cache memory controller using a store-through system if the stored flag in said cache memory controller related to the storage location of the private cache memory where said corresponding block of data is stored indicates that said block of data is to be controlled using a store-through system, and updating said block of data stored in said main storage using a store-in system if the stored flag in said cache memory controller related to the storage location of the private cache memory where said block of data is stored indicates that the block of data is to be controlled using a store-in system.

Claim 4

A cache memory control method for use in an information processing apparatus composed of a main storage, for storing a plurality of blocks of data, and a plurality of processor units, said processor units each including a processor having a control status register for storing information about the processor's control status, a private cache memory associated with said processor and said main storage, and a cache memory controller associated with said processor and said private cache memory, said method comprising the steps of: a) providing a read-request for reading a block of data from one of said processors to the cache memory controller associated therewith, said read-request including information indicating an address for designating a storage location of the main storage where the data to be read is stored; b) in the cache memory controller which has received said read-request from the associated processor, loading the block of data from a storage location of said main storage, designated by the address information included in said read-request, into a storage location of the associated private cache memory if said block of data is not already present in the private cache memory, discriminating, based on information in said control status register, whether the requested data is to be controlled using a store-in system or a store-through system, and storing a flag indicating the discriminated system in relation to the storage location of the associated private cache memory where said block of data was loaded; and c) updating a block of data stored in said main storage with a corresponding block of data stored in the private cache memory associated with said cache memory controller using a store-through system if the stored flag in said cache memory controller related to the storage location of the private cache memory where said corresponding block of data is stored indicates that said block of data is to be controlled using a store-through system, and updating said block of data stored in said main storage using a store-in system if the stored flag in said cache memory controller related to the storage location of the private cache memory where said block of data is stored indicates that the block of data is to be controlled using a store-in system.

Claim 5

A cache memory control method according to claim 2, in which said main storage includes a common area to be utilized by a plurality of said processors and a plurality of private areas, each private area corresponding to one of said processors to be used exclusively by the corresponding processor; and said discriminating step comprising discriminating that said data block is to be controlled using said store-through system if said information in the control status register indicating the data requested by the read-request is stored in said common area, and discriminating that said data block is to be controlled using said store-in system if said information in said control status block indicating the data block is stored in a private area.

Claim 6

A cache memory control method according to claim 2, wherein said discriminating step comprises discriminating that the data block is to be controlled using said store-through system if said information in the control status register is program code data, and discriminating that said data block is to be controlled using said store-in system if said information in said control status register indicating the data is not program code data.

Claim 7

A cache memory control method according to claim 4, in which said main storage is divided into a plurality of pages or segments, each of said pages or segments including a plurality of blocks of data; and in which said discriminating step comprises discriminating according to the identity of the page or segment including the data requested by the read-request, said identity being indicated by said information in said control status register.

Claim 8

An information processing apparatus comprising: (a) a main storage for storing a plurality of data; and (b) a plurality of processor units each including a processor, a private cache memory coupled to said processor, and a cache memory controller which controls said cache memory and is coupled to said cache memory and said processor; 1) each processor comprising: a) means for generating a read-request for reading data from said main storage, said read-request including information indicating whether the data requested by the read request is to be controlled using a store-through system or a store-in system; b) a control status register for storing information about the processor's control status; and c) means for outputting the generated read-request to the cache memory controller associated with that processor; and 2) each cache memory controller comprising: a) means for storing a plurality of flags, each flag corresponding to a respective one of the data stored in the private cache memory associated with the cache memory controller and each indicating whether the corresponding data is to be controlled using the store-through system or the store-in system; b) means for loading data requested by a received read-request from said main storage into the cache memory associated with the cache memory controller if the requested data is not present already in the associated cache memory; c) means for setting the flag corresponding to the data loaded in the associated cache memory according to said information, included in the received read-request which caused the loading, in said control status register; and d) means for controlling an operation of updating a storage location of said main storage with the data stored in a corresponding storage location of the cache memory associated with the cache memory controller using the store-through system if the flag corresponding to the data stored in said corresponding storage location of the cache memory indicates that the data is to be controlled using the store-through system, and controlling said updating operation using said store-in system if said stored flag corresponding to the data stored in said corresponding storage location of the cache memory indicates that the data is to be controlled using the stored-in system.

Claim 9

An information processing apparatus comprising: (a) a main storage for storing a plurality of data; and (b) a plurality of processor units each including a processor, a private cache memory coupled to said processor, and a cache memory controller which controls said cache memory and is coupled to said cache memory and said processor; 1) each processor comprising: a) means for generating a read-request for reading data from said main storage, said read-request including information indicating whether the data requested by the read request is to be controlled using a store-through system or a store-in system; b) a control status register for storing information about the processor's control status; and c) means for outputting the generated read-request to the cache memory controller associated with that processor; and 2) each cache memory controller comprising: a) means for storing a plurality of flags, each flag corresponding to a respective one of the data stored in the private cache memory associated with the cache memory controller and each indicating whether the corresponding data is to be controlled using the store-through system or the store-in system; b) means for loading data requested by a received read-request from said main storage into the cache memory associated with the cache memory controller if the requested data is not present already in the associated cache memory; c) means for setting the flag corresponding to the data loaded in the associated cache memory according to said information, included in the received read-request which caused the loading, in said control status register; and d) means for controlling an operation of updating a storage location of said main storage with the data stored in a corresponding storage location of the cache memory associated with the cache memory controller using the store-through system if the flag corresponding to the data stored in said corresponding storage location of the cache memory indicates that the data is to be controlled using the store-through system, and controlling said updating operation using said store-in system if said stored flag corresponding to the data stored in said corresponding storage location of the cache memory indicates that the data is to be controlled using the stored-in system.

Claim 10

An information processing apparatus according to claim 6, wherein: said means for setting the flag includes means for setting the flag indicating that the data requested by the read request is to be controlled using the store-through system if the information in said control status register indicates that the data is program code data, and for setting the flag indicating that the data requested by the read request is to be controlled using the store-in system if the information in said control status register indicates that the data is not program code data.

Claim 11

An information processing apparatus according to claim 6, wherein: said main storage includes a common memory area utilized for a plurality of said processors and a plurality of private memory areas, each private memory area respectively corresponding to one of said processors and being utilized exclusively for the corresponding processor; and said means for setting the flag includes means for setting the flag which indicates that the data requested by the read-request is to be controlled using the store-through system if the information in said control status register indicates that the data is stored in said common memory area of the main storage and for setting the flag which indicates that the data requested by the read-request is to be controlled using the store-in system if the information in said control status register indicates that the data is stored in the private area for the processor which issued the read-request.

Claim 12

An information processing apparatus for performing a plurality of processes, said information processing apparatus comprising: (a) a main storage for storing a plurality of data divided into a plurality of blocks of data; and (b) a plurality of processor units each including a processor for executing a process or processes, a private cache memory coupled to said processor and a cache memory controller which controls said cache memory and is coupled to said cache memory and said processor; 1) each processor comprising: a) means for generating a read-request for reading data from said main storage, said read-request including information indicating whether the data requested by the read request is to be controlled using a store-through system or a store-in system; b) a control status register for storing information about the processor's control status; and c) means for outputting the generated read-request to the cache memory controller associated with that processor; and 2) each cache memory controller comprising: a) means for loading a block of data including the data requested by a received read-request from said main storage into the cache memory associated with the cache memory controller if the requested block of data is not present already in the associated cache memory; b) means for storing a plurality of flags each of which corresponds to a respective one of the blocks of data stored in the cache memory associated with the cache memory controller, each of said flags indicating whether the corresponding block of data is to be controlled using said store-through system or store-in system; c) means for setting the flag corresponding to the block of data loaded in the associated cache memory according to said information included in the received read-request which caused the loading; and d) means for controlling an operation of updating a storage location of said main storage with the block of data stored in the corresponding storage location of the cache memory associated with the cache memory controller using the store-through system if the flag corresponding to said corresponding block of data stored in said corresponding storage location of the cache memory indicates that the block of data is to be controlled using the store-in system.

Claim 13

An information processing apparatus for performing a plurality of processes, said information processing apparatus comprising: (a) a main storage for storing a plurality of data divided into a plurality of blocks of data; and (b) a plurality of processor units each including a processor for executing a process or processes, a private cache memory coupled to said processor and a cache memory controller which controls said cache memory and is coupled to said cache memory and said processor; 1) each processor comprising: a) means for generating a read-request for reading data from said main storage, said read-request including information indicating whether the data requested by the read request is to be controlled using a store-through system or a store-in system; b) a control status register for storing information about the processor's control status; and c) means for outputting the generated read-request to the cache memory controller associated with that processor; and 2) each cache memory controller comprising: a) means for loading a block of data including the data requested by a received read-request from said main storage into the cache memory associated with the cache memory controller if the requested block of data is not present already in the associated cache memory; b) means for storing a plurality of flags each of which corresponds to a respective one of the blocks of data stored in the cache memory associated with the cache memory controller, each of said flags indicating whether the corresponding block of data is to be controlled using said store-through system or store-in system; c) means for setting the flag corresponding to the block of data loaded in the associated cache memory according to said information included in the received read-request which caused the loading; and d) means for controlling an operation of updating a storage location of said main storage with the block of data stored in the corresponding storage location of the cache memory associated with the cache memory controller using the store-through system if the flag corresponding to said corresponding block of data stored in said corresponding storage location of the cache memory indicates that the block of data is to be controlled using the store-in system.

Claim 14

An information processing apparatus according to claim 9, wherein: said means for setting the flag includes means for setting the flag indicating that the data requested by the read request is to be controlled using the store-through system if the information in said control status register indicates that the data is program code data and for setting the flag indicating that the data requested by the read request is to be controlled using the store-in system if the information in said control status register indicates that the data is not program code data.

Claim 15

An information processing apparatus according to claim 9, wherein: at least part of said main storage is divided into a plurality of pages, each of said pages including a plurality of said blocks of data; and said means for setting the flag includes means for setting the flag which indicates that the data requested by the read-request is to be controlled using a store-through system or a store-in system according to the page including the data requested by the read-request, said page being indicated by the information in said control status register.

Claim 16

An information processing apparatus according to claim 9, wherein: at least part of said main storage is divided into a common segment utilized for a plurality of said processes and a plurality of private segments, each of said private segments respectively corresponding to one of said processes and being utilized exclusively for the corresponding process; and said means for setting the flag includes means for setting the flag which indicates that the data requested by the read-request is to be controlled using the store-through system if the information in said control status register indicates that the segment including the requested data is said common segment, and for setting the flag which indicates the data requested by the read-request is to be controlled using the store-in system if the information in said control status register indicates that the segment including the requested data is a private segment.

Claim 17

An information processing apparatus according to claim 9, wherein: at least a part of said main storage is divided into a primary space for storing a program utilized for a plurality of said processes and a plurality of secondary spaces, each of said secondary spaces respectively corresponding to one of said processes and being utilized exclusively for the corresponding process; and said means for setting the flag includes means for setting the flag which indicates that the data requested by the read-request is to be controlled using the store-through system if the information in said control status register indicates that the space including the requested data is said primary space, and for setting the flag which indicates the data requested by the read-request is to be controlled using the store-in system if the information in said control status register indicates that the space including the requested data is a secondary space.

Claim 18

An information processing apparatus according to claim 9, further comprising a main storage control unit associated with said main storage, said main storage control unit including: 1) means for storing a plurality of flags, each flag corresponding to a respective one of the blocks of data stored in the main storage, each of said flags indicating whether the corresponding block of data is to be controlled using the store-through system or the store-in system; 2) means for controlling the block of data in said main storage which corresponds to a block of data being loaded in one cache memory, but not into another cache memory, if the stored flag corresponding to the block of data indicates that the corresponding block of data is to be controlled using the store-in system; and 3) means for nullifying a block of data in a cache memory which corresponds to a block of data updated in main storage, if the stored flag corresponding to the updated block of data indicates that the corresponding block of data is to be controlled using the store-through system.

Claim 19

An information processing apparatus according to claim 1, wherein the information stored in said control storage register indicates an attribute of the data loaded into the cache memory.

Claim 20

An information processing apparatus according to claim 1, wherein the information stored in said control storage register indicates an attribute of the storage area.

Claim 21

An information processing apparatus according to claim 16 further comprising: a main storage control unit associated with said main storage, said main storage control unit including means for giving to data stored in the main storage and loaded into any one of the cache memories an attribute corresponding to the attribute given by said discriminating means.

Claim 22

An information processing apparatus according to claim 1 further comprising: a main storage control unit associated with said main storage, said main storage control unit including means for giving to data stored in the main storage and loaded into any one of the cache memories an attribute corresponding to the attribute given by said discriminating means.

Claim 23

An information processing apparatus according to claim 6, further comprising a main storage control unit associated with said main storage, said main storage control unit including means for storing a plurality of flags, each flag corresponding to a respective one of the blocks of data stored in the main storage, each of said flags indicating whether the corresponding block of data is to be controlled using the store-through system or the store-in system.