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US5353425A
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US
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Methods and apparatus for implementing a pseudo-LRU cache memory replacement scheme with a locking feature
Assignee: Sun Microsystems Inc
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Filing: 1992-04-29
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Granted: 1994-10-04
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Expires: 2012-04-29
Abstract
Abstract In a memory system having a main memory and a faster cache memory, a cache memory replacement scheme with a locking feature is provided. Locking bits associated with each line in the cache are supplied in the tag table. These locking bits are preferably set and reset by the application program/process executing and are utilized in conjunction with cache replacement bits by the cache controller to determine the lines in the cache to replace. The lock bits and replacement bits for a cache line are "ORed" to create a composite bit for the cache line. If the composite bit is set the cache line is not removed from the cache. When deadlock due to all composite bits being set will result, all replacement bits are cleared. One cache line is always maintained as non-lockable. The locking bits "lock" the line of data in the cache until such time when the process resets the lock bit. By providing that the process controls the state of the lock bits, the intelligence and knowledge the process contains regarding the frequency of use of certain memory locations can be utilized to provide a more efficient cache.
Inventors
- 👤 Adam Malamy
- 👤 Rajiv N. Patel
- 👤 Norman M. Hayes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 08:35
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/12; G06F12/121; G06F12/126; G06F13/00; G06F13/14; G06F12/123; G06F12/125
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
371 words
In a computer system comprising master devices including a central processing unit (CPU), and a memory system comprising a main memory having a plurality of lines and a cache memory wherein a subset of the lines of main memory are stored in the cache memory for fast access by a master device issuing a request for access to said memory system, an apparatus for securing selected lines of main memory in cache memory comprising: a tag table comprising tag bits for each cache line, at least one replacement bit for each cache line, and at least one lock bit for each cache line of the cache memory, said tag bits identifying the line of main memory located in cache memory; a composite bit for each cache line, each composite bit comprising a logical OR of said at least one replacement bit for a cache line and said at least one lock bit for a cache line; replacement bit circuitry for controlling the states of the at least one replacement bit for each cache line located in the tag table, said replacement bit circuitry setting the at least one replacement bit for a cache line when said cache line is accessed; lock bit circuitry for controlling the states of the at least one lock bit for each cache line located in the tag table; composite bit circuitry for monitoring the composite bits to prohibit all composite bits from being set by clearing the at least one replacement bit for each cache line to avoid deadlock; cache memory replacement circuitry for replacing a line of memory located in the cache memory with a different line of memory, said cache memory replacement circuitry prohibited from replacing a line of cache memory if the corresponding composite bit is set, said cache memory replacement circuitry controlled such that by setting the corresponding at least one lock bit for a cache line in the tag table, a line of memory located in the cache memory is secured in the cache memory regardless of a cache replacement algorithm, and by setting the corresponding at least one replacement bit for a cache line in the tag table, a cache memory line is not replaced regardless of the lock bit.
Claim 2
Dependent Claim
371 words
In a computer system comprising master devices including a central processing unit (CPU), and a memory system comprising a main memory having a plurality of lines and a cache memory wherein a subset of the lines of main memory are stored in the cache memory for fast access by a master device issuing a request for access to said memory system, an apparatus for securing selected lines of main memory in cache memory comprising: a tag table comprising tag bits for each cache line, at least one replacement bit for each cache line, and at least one lock bit for each cache line of the cache memory, said tag bits identifying the line of main memory located in cache memory; a composite bit for each cache line, each composite bit comprising a logical OR of said at least one replacement bit for a cache line and said at least one lock bit for a cache line; replacement bit circuitry for controlling the states of the at least one replacement bit for each cache line located in the tag table, said replacement bit circuitry setting the at least one replacement bit for a cache line when said cache line is accessed; lock bit circuitry for controlling the states of the at least one lock bit for each cache line located in the tag table; composite bit circuitry for monitoring the composite bits to prohibit all composite bits from being set by clearing the at least one replacement bit for each cache line to avoid deadlock; cache memory replacement circuitry for replacing a line of memory located in the cache memory with a different line of memory, said cache memory replacement circuitry prohibited from replacing a line of cache memory if the corresponding composite bit is set, said cache memory replacement circuitry controlled such that by setting the corresponding at least one lock bit for a cache line in the tag table, a line of memory located in the cache memory is secured in the cache memory regardless of a cache replacement algorithm, and by setting the corresponding at least one replacement bit for a cache line in the tag table, a cache memory line is not replaced regardless of the lock bit.
Claim 3
Dependent Claim
63 words
The apparatus as set forth in claim 1, wherein said cache memory replacement circuitry selects a line of the cache memory with a clear composite bit to replace, and said cache memory replacement circuitry clears said at least one replacement bit for each cache line if only one cache line has a clear composite bit to prohibit all composite bits from being set.
Claim 4
Dependent Claim
29 words
The apparatus as set forth in claim 2, wherein said lock bit circuitry identifies at least one predetermined line of the cache as non-lockable such that deadlock is avoided.
Claim 5
Dependent Claim
18 words
The apparatus as set forth in claim 1, wherein said cache memory replacement circuitry comprises a cache controller.
Claim 6
Dependent Claim
37 words
The apparatus as set forth in claim 1, wherein said lock bit circuitry for controlling the state of the at least one lock bit for each cache line is controlled by instructions issued by the master device.
Claim 7
Dependent Claim
42 words
The apparatus as set forth in claim 1, wherein said lock bit circuitry for controlling the state of the at least one lock bit for each cache line is controlled by instructions issued by an application process executing on the computer system.
Claim 8
Dependent Claim
42 words
The apparatus as set forth in claim 5, wherein said instructions are processed by an operating system of the computer system to issue commands to a cache controller to set or rest the at least one lock bit for a cache line.
Claim 9
Dependent Claim
49 words
The apparatus as set forth in claim 5, further comprising a compiler to compile a program to generate compiled code to be executed, said compiler evaluating the program and inserting commands to set and reset the at least one lock bit for a cache line in the compiled code.
Claim 10
Dependent Claim
331 words
In a computer system comprising master devices including a central processing unit (CPU), and a memory system comprising a main memory having a plurality of lines and a cache memory and a tag table associated with the cache memory, wherein a subset of the lines of main memory are stored in the cache memory for fast access by a master device issuing a request for access to said memory system, said tag table comprising tag bits, said tag bits identifying lines of main memory located in the cache memory, a method for securing selected lines of main memory in the cache memory comprising: providing at least one replacement bit for each cache line and at least one lock bit for each cache line of the cache memory in the tag table; combining the at least one replacement bit for each cache line and the at least one lock bit for each cache line with a logical OR to produce a composite bit for each cache line; controlling the state of the at least one replacement bit for each cache line and the state of the at least one lock bit for each cache line located in the tag table; monitoring the composite bit of each cache line to prohibit all composite bits from being set by clearing the at least one replacement bit for each cache line to avoid deadlock; and replacing a line of cache memory with a different line of memory, only if the cache memory line has a clear composite bit, said replacing a line of cache memory controlled such that by setting the corresponding at least one lock bit for a cache line in the tag table, lines of memory located in the cache memory are secured in the cache memory regardless of a cache replacement algorithm used, and by setting the corresponding at least one replacement bit for a cache line in the tag table, cache memory lines are not replaced regardless of the lock bit.
Claim 11
Dependent Claim
331 words
In a computer system comprising master devices including a central processing unit (CPU), and a memory system comprising a main memory having a plurality of lines and a cache memory and a tag table associated with the cache memory, wherein a subset of the lines of main memory are stored in the cache memory for fast access by a master device issuing a request for access to said memory system, said tag table comprising tag bits, said tag bits identifying lines of main memory located in the cache memory, a method for securing selected lines of main memory in the cache memory comprising: providing at least one replacement bit for each cache line and at least one lock bit for each cache line of the cache memory in the tag table; combining the at least one replacement bit for each cache line and the at least one lock bit for each cache line with a logical OR to produce a composite bit for each cache line; controlling the state of the at least one replacement bit for each cache line and the state of the at least one lock bit for each cache line located in the tag table; monitoring the composite bit of each cache line to prohibit all composite bits from being set by clearing the at least one replacement bit for each cache line to avoid deadlock; and replacing a line of cache memory with a different line of memory, only if the cache memory line has a clear composite bit, said replacing a line of cache memory controlled such that by setting the corresponding at least one lock bit for a cache line in the tag table, lines of memory located in the cache memory are secured in the cache memory regardless of a cache replacement algorithm used, and by setting the corresponding at least one replacement bit for a cache line in the tag table, cache memory lines are not replaced regardless of the lock bit.
Claim 12
Dependent Claim
52 words
The method as set forth in claim 9, wherein the step of controlling the state of the at least one lock bit for each cache line comprises providing instructions that set or reset the at least one lock bit for a cache line in an application process executing in the computer system.
Claim 13
Dependent Claim
71 words
The method as set forth in claim 10, wherein the step of controlling the state of the at least one lock bit for each cache line further comprises issuing commands that set or reset the at least one lock bit for a cache line in the tag table when an instruction in the application program to set or reset the at least one lock bit for a cache line is executed.
Claim 14
Dependent Claim
131 words
The method as set forth in claim 9, wherein the at least one lock bit for a cache line is set or reset during the execution of a program on the computer system, said method further comprising the step of compiling the program into compiled code to be executed, said step comprising: evaluating the program to determine when the at least one lock bit for a cache line is to be set or reset for certain lines of memory placed in the cache memory; inserting commands to set or reset the at least one lock bit for a cache line in the cache memory into the compiled code; and generating compiled code comprising the program and commands to set or reset the at least one lock bit for a cache line.
Claim 15
Dependent Claim
353 words
In a computer system comprising master devices including a central processing unit (CPU), and a memory system comprising a main memory having a plurality of lines and a cache memory wherein a subset of the lines of main memory are stored in the cache memory for fast access by a master device issuing a request for access to said memory system, an apparatus for securing selected lines of main memory in cache memory comprising: a tag table comprising tag bits for each cache line, at least one replacement bit for each cache line, and at least one lock bit for each cache line of the cache memory, said tag bits identifying the line of main memory located in cache memory; a composite bit for each cache line, each composite bit comprising a logical OR of said at least one replacement bit for a cache line and said at least one lock bit for a cache line; an operating system for issuing commands to set or reset the at least one lock bit for a cache line located in the tag table; and a cache controller to control the contents of the cache memory and the tag table, said cache controller executing a replacement algorithm to replace a line of memory located in the cache memory with a different line of memory and updating the tag table, said cache controller prohibited from replacing a line of memory in the cache if the corresponding composite bit for said line of memory in the cache in the tag table is set, said cache controller clearing said at least one replacement bit for each cache line if all of said composite bits are set, said cache controller controlled such that by setting the corresponding at least one lock bit for a cache line in the tag table, lines of memory located in the cache memory are secured in the cache memory regardless of a cache replacement algorithm used, and by setting the corresponding at least one replacement bit for a cache line in the tag table, cache memory lines are not replaced regardless of the lock bit.
Claim 16
Dependent Claim
353 words
In a computer system comprising master devices including a central processing unit (CPU), and a memory system comprising a main memory having a plurality of lines and a cache memory wherein a subset of the lines of main memory are stored in the cache memory for fast access by a master device issuing a request for access to said memory system, an apparatus for securing selected lines of main memory in cache memory comprising: a tag table comprising tag bits for each cache line, at least one replacement bit for each cache line, and at least one lock bit for each cache line of the cache memory, said tag bits identifying the line of main memory located in cache memory; a composite bit for each cache line, each composite bit comprising a logical OR of said at least one replacement bit for a cache line and said at least one lock bit for a cache line; an operating system for issuing commands to set or reset the at least one lock bit for a cache line located in the tag table; and a cache controller to control the contents of the cache memory and the tag table, said cache controller executing a replacement algorithm to replace a line of memory located in the cache memory with a different line of memory and updating the tag table, said cache controller prohibited from replacing a line of memory in the cache if the corresponding composite bit for said line of memory in the cache in the tag table is set, said cache controller clearing said at least one replacement bit for each cache line if all of said composite bits are set, said cache controller controlled such that by setting the corresponding at least one lock bit for a cache line in the tag table, lines of memory located in the cache memory are secured in the cache memory regardless of a cache replacement algorithm used, and by setting the corresponding at least one replacement bit for a cache line in the tag table, cache memory lines are not replaced regardless of the lock bit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-03 | 1998-04-04 | 1998-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-03 | 2002-04-04 | 2002-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-03 | 2006-04-04 | 2006-10-04 | $7700.00 | Window Closed / Lapsed |