EP0459233A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Selectively locking memory locations within a microprocessor's on-chip cache
Assignee: National Semiconductor Corp
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Filing: 1991-05-16
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Granted: —
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Expires: 2011-05-16
Abstract
Abstract A microprocessor architecture that includes capabilities for locking individual entries into its integrated instruction cache and data cache while leaving the remainder of the cache unlocked and available for use in capturing the microprocessor's dynamic locality of reference. The microprocessor also includes the capability for locking instruction cache entries without requiring that the instructions be executed during the locking process.
Inventors
- 👤 Donald B. Alpert
- 👤 Oved Oz
- 👤 Gideon Intrater
- 👤 Reuven Marko
- 👤 Alon Shacham
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 02:11
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/12; G06F12/121; G06F12/126; G06F9/00; G06F9/06; G06F9/30; G06F9/32
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
89 words
A microprocessor that processes information retrieved from an external memory via a system bus or from an internal storage element, the microprocessor comprising: (a) a cache memory comprising a plurality of storage locations for storing information entries to be processed by the microprocessor; (b) means for replacing information entries stored in the internal storage element with information entries retrieved from the external memory; and (c) means for locking selected storage locations in the internal storage element memory to prevent replacement of information entries stored in the selected storage locations.
Claim 2
Dependent Claim
91 words
A microprocessor that executes instructions and processes data retrieved from an external memory via a system bus or from an integrated cache memory, the microprocessor comprising: (a) an instruction cache comprising a plurality of storage locations for storing instruction entries comprising instructions to be executed by the microprocessor; (b) means for replacing instruction entries stored in the instruction cache with instruction entries retrieved from the external memory; and (c) means for locking selected storage locations in the instruction cache to prevent replacement of instruction entries stored in the selected storage locations.
Claim 3
Dependent Claim
44 words
A microprocessor as in claim 2 wherein the means for locking selected storage locations in the instruction cache comprises a configuration register that enables or disables various operating modes for the microprocessor, including the locking of the selected storage locations in the instruction cache.
Claim 4
Dependent Claim
33 words
A microprocessor as in claim 3 wherein the configuration register includes means for storing a bit that controls whether a storage location which receives an instruction entry retrieved from external memory is locked.
Claim 5
Dependent Claim
33 words
A microprocessor as in claim 2 wherein each instruction entry stored in the instruction cache includes a bit that indicates whether the storage location in which the instruction entry is stored is locked.
Claim 6
Dependent Claim
19 words
A microprocessor as in claim 2 and further including means for invalidating instruction entries stored in unlocked storage locations.
Claim 7
Dependent Claim
29 words
A microprocessor as in claim 2 and further including means for invalidating all instruction entries stored in the instruction cache, including instruction entries stored in the selected storage locations.
Claim 8
Dependent Claim
33 words
A microprocessor as in claim 2 and further including means for locking a selected storage location without the microprocessor executing the instruction included in the instruction entry stored in the selected storage location.
Claim 9
Dependent Claim
91 words
A microprocessor that executes instructions and process data retrieved from an external memory via a system bus or from an integrated cache memory, the microprocessor comprising: (a) a data cache comprising a plurality of storage locations for storing data entries comprising data to be processed by the microprocessor; (b) means for replacing data entries stored in the data cache with data entries retrieved from the external memory; and (c) means for locking selected storage locations in the data cache to prevent replacement of data entries stored in the selected storage locations.
Claim 10
Dependent Claim
44 words
A microprocessor as in claim 9 wherein the means for locking selected storage locations in the data cache comprises a configuration register that enables or disables various operating modes for the microprocessor, including the locking of the selected storage locations in the data cache.
Claim 11
Dependent Claim
34 words
A microprocessor as in claim 10 wherein the configuration register includes means for storing a bit that controls whether a storage location which receives a data entry retrieved from external memory will be locked.
Claim 12
Dependent Claim
33 words
A microprocessor as in claim 9 wherein each data entry stored in the data cache includes a bit that indicates whether the storage location in which the data entry is stored is locked.
Claim 13
Dependent Claim
19 words
A microprocessor as in claim 9 and further including means for invalidating data entries stored in unlocked storage locations.
Claim 14
Dependent Claim
29 words
A microprocessor as in claim 9 and further including means for invalidating all data entries stored in the data cache, including data entries stored in the selected storage locations.
References Cited (Backward Citations)
No citation records indexed.
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