EP0278478A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Cache memory system with improved re-writing address determination scheme
Assignee: NEC Corp
•
Filing: 1988-02-09
•
Granted: —
•
Expires: 2008-02-09
Abstract
Abstract A cache memory system having an improved area addressing scheme for rewriting is disclosed. The cache memory system comprises a cache memory having a plurality of memory areas, means for designating the least recently accessed area by a CPU, means for detecting that the least recently accessed memory area is not designated and means for forcibly selecting a predetermined one memory area for rewriting when the least recently accessed memory area is not designed.
Inventors
- 👤 Hidehiro Asai
- 👤 Kenichi Echigoya
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 10:07
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/12; G06F12/121; G06F12/123; G06F12/125
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
97 words
A system comprising a memory circuit having a plurality of memory areas, means for accessing one of said memory areas, means for determining the least recently accessed memory area among said memory areas, means for writing date from the outside into the least recently accessed memory area determined by said determining means, means for detecting that said determining means does not designate the least recently accessed memory area, and means for forcibly designating a predetermined one of said memory areas for writing when said detecting means detects that the least recently accessed memory area is not designated.
Claim 2
Independent Claim
97 words
A system comprising a memory circuit having a plurality of memory areas, means for accessing one of said memory areas, means for determining the least recently accessed memory area among said memory areas, means for writing date from the outside into the least recently accessed memory area determined by said determining means, means for detecting that said determining means does not designate the least recently accessed memory area, and means for forcibly designating a predetermined one of said memory areas for writing when said detecting means detects that the least recently accessed memory area is not designated.
Claim 3
Dependent Claim
37 words
The system according to Claim 1, further comprising means for designating the most recently accessed memory area among said memory areas and said detecting means further detecting that the most recently accessed memory area is not designated.
Claim 4
Dependent Claim
14 words
The system according to Claim 1, further comprising a plurality of state storage elements.
Claim 5
Independent Claim
171 words
A system comprising a central processing unit, a main memory, a cache memory operable at a speed higher than said main memory and having a memory capacity smaller than said main memory, said cache memory having a plurality of memory areas, a first bus coupled between said central processing unit and said cashe memory, a second bus coupled between said cache memory and said main memory, said central processing unit accessing one of said memory areas, and a control circuit for writing data stored in said main memory into one of said memory areas, said control circuit including means for designating the least recently accessed memory area in said cache memory, means for detecting that the least recently accessed memory area is not designated, and means for selecting one of said memory areas in accordance with the state of said designating means when said designating means designates the least recently accessed memory area and a predetermined one of said memory areas when the least recently accessed memory area is not designated.
Claim 6
Independent Claim
171 words
A system comprising a central processing unit, a main memory, a cache memory operable at a speed higher than said main memory and having a memory capacity smaller than said main memory, said cache memory having a plurality of memory areas, a first bus coupled between said central processing unit and said cashe memory, a second bus coupled between said cache memory and said main memory, said central processing unit accessing one of said memory areas, and a control circuit for writing data stored in said main memory into one of said memory areas, said control circuit including means for designating the least recently accessed memory area in said cache memory, means for detecting that the least recently accessed memory area is not designated, and means for selecting one of said memory areas in accordance with the state of said designating means when said designating means designates the least recently accessed memory area and a predetermined one of said memory areas when the least recently accessed memory area is not designated.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.