US5352629A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for self-alignment and planarization of semiconductor chips attached by solder die adhesive to multi-chip modules
Assignee: Lockheed Martin Corp
•
Filing: 1993-01-19
•
Granted: 1994-10-04
•
Expires: 2013-01-19
Abstract
Abstract A method for attaching a chip to a substrate includes providing the substrate with an outer layer of an electrical conductor which is not wettable by solder and which has a window exposing an inner layer of electrical conductor that is wettable by solder. A solder preform is placed on the window exposing the inner layer, and the chip is placed on the solder preform. The substrate is then heated so as to melt the solder preform. To achieve planarity, the substrate is be positioned in a pressurizing chamber with a film overlay having higher pressure above the film overlay than underneath the overlay, and heated above the melting point of the solder.
Inventors
- 👤 Kyung W. Paik
- 👤 William A. Hennessy
- 👤 Wolfgang Daum
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 09:52
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/67; H10W70/68; H10W70/682; H10W72/00; H10W72/071; H10W72/0711; H10W72/07125; H10W72/07141; H10W72/073; H10W72/07331; H10W72/07332; H10W72/07333; H10W72/07336; H10W72/30; H10W72/351; H10W72/352; H10W72/353; H10W72/354; H10W90/00; H10W90/701; H10W90/731; H10W90/734
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
206 words
A method for attaching at least one semiconductor chip, with an electrical conductor disposed on an underside of each of said at least one chip, to a substrate having a surface, to cause self-alignment and PLANARIZATION of said at least one chip, comprising: providing on said substrate surface an inner layer of electrical conductor having solder wettability; providing on said inner layer an outer layer of electrical conductor having solder nonwettability and having at least one window therein exposing said inner layer, said at least one window having a length and width substantially equal to an associated length and width of said at least one chip; placing a solder preform on each respective one of said at least one window; placing a chip on each respective one of said solder preforms; placing said substrate into a structure capable of applying isostatic pressure; overlaying said substrate and said at least one chip with a dielectric film layer; applying pressure over said dielectric film layer; and subsequently heating said substrate above the melting point of said solder preforms to align each of said at least one chip within said at least one window, and substantially simultaneously to planarize said at least one chip with respect to said surface.
Claim 2
Independent Claim
206 words
A method for attaching at least one semiconductor chip, with an electrical conductor disposed on an underside of each of said at least one chip, to a substrate having a surface, to cause self-alignment and PLANARIZATION of said at least one chip, comprising: providing on said substrate surface an inner layer of electrical conductor having solder wettability; providing on said inner layer an outer layer of electrical conductor having solder nonwettability and having at least one window therein exposing said inner layer, said at least one window having a length and width substantially equal to an associated length and width of said at least one chip; placing a solder preform on each respective one of said at least one window; placing a chip on each respective one of said solder preforms; placing said substrate into a structure capable of applying isostatic pressure; overlaying said substrate and said at least one chip with a dielectric film layer; applying pressure over said dielectric film layer; and subsequently heating said substrate above the melting point of said solder preforms to align each of said at least one chip within said at least one window, and substantially simultaneously to planarize said at least one chip with respect to said surface.
Claim 3
Dependent Claim
29 words
The method of claim 1, further including the step of providing chip wells in said substrate prior to providing said substrate with said outer layer and said inner layer.
Claim 4
Dependent Claim
19 words
The method of claim 2, wherein the step of providing chip wells comprises providing chip wells with slanted sidewalls.
Claim 5
Dependent Claim
29 words
The method of claim 2, further including the step of applying a vacuum under said dielectric film layer during the step of applying pressure over said dielectric film layer.
Claim 6
Dependent Claim
13 words
The method of claim 4, wherein said dielectric film layer comprises a polyimide.
Claim 7
Dependent Claim
25 words
The method of claim 4, further including the step of cooling said substrate while still applying said vacuum after the step of heating said substrate.
Claim 8
Dependent Claim
26 words
The method of claim 4, further including the steps of cooling said substrate after the step of heating said substrate, and thereafter removing said dielectric layer.
Claim 9
Independent Claim
202 words
A method for attaching at least one semiconductor chip, each with an electrical conductor disposed on an underside thereof, to a substrate having a surface, and having chip wells therein, causing chip attachment, chip alignment, and chip planarization substantially simultaneously, comprising: providing on said substrate surface an inner layer of electrical conductor having solder wettability; providing on said inner layer an outer layer of an electrical conductor having solder nonwettability and having at least one window therein exposing said inner layer, said at least one window having a length and width substantially equal to an associated length and width of said at least one chip; placing a solder preform on each respective one of said at least one window; placing a chip on each respective one of said solder preforms; placing said substrate into a structure capable of applying isostatic pressure; overlaying said substrate and said at least one chip with a dielectric film layer; applying pressure over said dielectric film layer; and subsequently heating said substrate above the melting point of said solder preforms to cause each of said at least one chip to be substantially simultaneously self-aligned within said at least one window and planarized with respect to said surface.
Claim 10
Independent Claim
202 words
A method for attaching at least one semiconductor chip, each with an electrical conductor disposed on an underside thereof, to a substrate having a surface, and having chip wells therein, causing chip attachment, chip alignment, and chip planarization substantially simultaneously, comprising: providing on said substrate surface an inner layer of electrical conductor having solder wettability; providing on said inner layer an outer layer of an electrical conductor having solder nonwettability and having at least one window therein exposing said inner layer, said at least one window having a length and width substantially equal to an associated length and width of said at least one chip; placing a solder preform on each respective one of said at least one window; placing a chip on each respective one of said solder preforms; placing said substrate into a structure capable of applying isostatic pressure; overlaying said substrate and said at least one chip with a dielectric film layer; applying pressure over said dielectric film layer; and subsequently heating said substrate above the melting point of said solder preforms to cause each of said at least one chip to be substantially simultaneously self-aligned within said at least one window and planarized with respect to said surface.
Claim 11
Dependent Claim
90 words
The method of claim 8, wherein the step of providing said outer layer having windows exposing said inner layer is performed so that each respective window has a length and width substantially equal to the length and width of a predetermined respective one of said chips; and the step of placing a solder preform on each respective one of said windows is performed so that each respective solder preform has a length and width substantially equal to the length and width of the respective window on which it is situated.
Claim 12
Dependent Claim
29 words
The method of claim 9, further including the step of applying a vacuum under said dielectric film layer during the step of applying pressure over said dielectric film layer.
Claim 13
Dependent Claim
12 words
The method of claim 10, wherein said chip wells have slanted sidewalls.
Claim 14
Dependent Claim
49 words
The method of claim 8, further including the steps of: applying a first solder flux on said inner layer through said windows prior to placing said preforms in said windows; and applying a second solder flux on said solder preforms prior to placing said chips on said solder preforms.
References Cited (Backward Citations)
US3401126A
Cited
US3424040A
Cited
US3869787A
Cited
US3887760A
Cited
US3919709A
Cited
JPS54131872A
Cited
US4810671A
Cited
US4783695A
Cited
US4933042A
Cited
WO1988003705A1
Cited
US5051811A
Cited
US5043296A
Cited
JPH01309343A
Cited
US5181648A
Cited
US5101550A
Cited
US5037778A
Cited
JPH0414852A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-03 | 1998-04-04 | 1998-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-03 | 2002-04-04 | 2002-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-03 | 2006-04-04 | 2006-10-04 | $7700.00 | Window Closed / Lapsed |