Method for precisely aligning circuit devices coarsely positioned on a substrate

Claim 2

In the fabrication of microminiature electronic apparatus, a method for precisely aligning semiconductor integrated circuit chips on a substrate, comprising the steps of: depositing on an area of the substrate a layer of fluid material, the area having planar dimensions essentially equal to those of the entire back surface of a chip, the fluid material capable of wetting the back surface of the chip but not capable of wetting the body of the chip; placing the back surface of the chip coarsely positioned on the deposited layer of fluid material, thereby allowing surface tension of the fluid material to precisely align the chip on the substrate.

Claim 3

In the fabrication of microminiature electronic apparatus, a method for precisely aligning semiconductor integrated circuit chips on a substrate, comprising the steps of: depositing on an area of the substrate a layer of fluid material, the area having planar dimensions essentially equal to those of the entire back surface of a chip, the fluid material capable of wetting the back surface of the chip but not capable of wetting the body of the chip; placing the back surface of the chip coarsely positioned on the deposited layer of fluid material, thereby allowing surface tension of the fluid material to precisely align the chip on the substrate.

Claim 4

In the fabrication of microminiature electronic apparatus, a method for precisely aligning semiconductor integrated circuit chips on a substrate, comprising the steps of: depositing on an area of the substrate a layer of fluid material, the area having planar dimensions essentially equal to those of the entire back surface of a chip, the fluid material capable of wetting the back surface of the chip but not capable of wetting the body of the chip; placing the back surface of the chip coarsely positioned on the deposited layer of fluid material, thereby allowing surface tension of the fluid material to precisely align the chip on the substrate.

Claim 5

In the fabrication of microminiature electronic apparatus, a method for precisely aligning semiconductor integrated circuit chips on a substrate, comprising the steps of: depositing a first layer of reflowable material on substanTially the entire back surface of a chip; depositing on an area of the substrate another layer of reflowable material, the area having planar dimensions essentially equal to those of the entire back surface of the chip; placing the chip face up and coarsely positioned on the deposited other layer of reflowable material; heating the layers of reflowable material until the layers become liquid and together form an interface layer between the chip and the substrate area; and cooling the interface layer after the chip aligns with the substrate area under influence of the surface tension of the liquified reflowable material.

Claim 6

In the fabrication of microminiature electronic apparatus, a method for precisely aligning semiconductor integrated circuit chips on a substrate, comprising the steps of: depositing a first layer of reflowable material on substanTially the entire back surface of a chip; depositing on an area of the substrate another layer of reflowable material, the area having planar dimensions essentially equal to those of the entire back surface of the chip; placing the chip face up and coarsely positioned on the deposited other layer of reflowable material; heating the layers of reflowable material until the layers become liquid and together form an interface layer between the chip and the substrate area; and cooling the interface layer after the chip aligns with the substrate area under influence of the surface tension of the liquified reflowable material.

Claim 7

The process as claimed in claim 2, wherein the interface layer formed during the heating step comprises a metal system which, after completion of the cooling step, permanently attaches the aligned chip to the substrate.

Claim 8

The process as claimed in claim 2, wherein the first deposited layer of reflowable material comprises an essentially volatile substance.

Claim 9

The process as claimed in claim 4, wherein the cooling step is delayed until the first deposited layer evaporates.

Claim 10

In the fabrication of microminiature electronic apparatus, a method for precisely aligning circuit elements on a substrate, comprising the steps of: forming a first circuit element on a surface of the substrate; depositing a first layer of solder on substantially the entire back surface of a second circuit element, the second circuit element having an electrical conductor extending in cantilevered fashion from an opposite surface thereof; depositing on an area of the surface of the substrate adjacent the first circuit element another layer of solder, the planar dimensions of the other layer essentially equal to those of the entire back surface of the second circuit element; placing the second circuit element coarsely positioned on the other layer of solder; heating the assembly until the layers of solder melt and together form an interface layer between the second circuit element and the substrate area; and cooling the interface layer of solder after the second circuit element aligns with the substrate area under influence of the surface tension of the molten solder, thereby aligning the first circuit element and the electrical conductor.

Claim 11

In the fabrication of microminiature electronic apparatus, a method for precisely aligning circuit elements on a substrate, comprising the steps of: forming a first circuit element on a surface of the substrate; depositing a first layer of solder on substantially the entire back surface of a second circuit element, the second circuit element having an electrical conductor extending in cantilevered fashion from an opposite surface thereof; depositing on an area of the surface of the substrate adjacent the first circuit element another layer of solder, the planar dimensions of the other layer essentially equal to those of the entire back surface of the second circuit element; placing the second circuit element coarsely positioned on the other layer of solder; heating the assembly until the layers of solder melt and together form an interface layer between the second circuit element and the substrate area; and cooling the interface layer of solder after the second circuit element aligns with the substrate area under influence of the surface tension of the molten solder, thereby aligning the first circuit element and the electrical conductor.

Claim 12

In the fabrication of microminiature electronic apparatus, a method for precisely aligning semiconductor integrated circuit chips on a substrate, comprising the steps of: forming a circuit element on a surface of the substrate; defining on the substrate an area having planar dimensions essentially equal to those of the entire back surface of a chip, the area precisely positioned with respect to said circuit element; depositing a layer of fluid material on the area; and placing the back surface of the chip coarsely positioned on the deposited layer of fluid material, the back surface of the chip wettable by the fluid material, the body of the chip non-wettable by the fluid material, thereby allowing surface tension of the fluid to precisely align the chip and circuit element.

Claim 13

In the fabrication of microminiature electronic apparatus, a method for precisely aligning semiconductor integrated circuit chips on a substrate, comprising the steps of: forming a circuit element on a surface of the substrate; defining on the substrate an area having planar dimensions essentially equal to those of the entire back surface of a chip, the area precisely positioned with respect to said circuit element; depositing a layer of fluid material on the area; and placing the back surface of the chip coarsely positioned on the deposited layer of fluid material, the back surface of the chip wettable by the fluid material, the body of the chip non-wettable by the fluid material, thereby allowing surface tension of the fluid to precisely align the chip and circuit element.

Claim 14

The process as claimed in claim 1, wherein the substrate area and the back surface of the chip are of rectangular shape.

Claim 15

The process as claimed in claim 2, wherein the substrate area and the back surface of the chip are of rectangular shape.

Claim 16

The process as claimed in claim 6, wherein the substrate area and the back surface of the second circuit element are of rectangular shape.