US5349552A
Expired / Lapsed
US
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Memory compiler with multiple selectable core elements
Assignee: Philips Semiconductors Inc
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Filing: 1991-12-20
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Granted: 1994-09-20
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Expires: 2011-12-20
Abstract
Abstract Methods and devices for efficiently using substrate space to form memory devices on integrated circuits, and in particular, in application specific integrated circuits. More particularly, a shared decoder and control logic are used for selectively accessing and addressing plural types of memory (e.g., RAM and ROM cells). Further, each memory cell of a memory array is programmed as a particular type of memory cell during circuit layout design. Therefore, specific rows, columns, or single bits of the memory cell array can be designated as specific types of memory.
Inventors
- 👤 Michael A. Zampaglione
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 07:18
CPC Classifications
G; G11; G11C; G11C8/00; G11C11/00; G11C11/005
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
101 words
A method for designing a memory array comprising the steps of: establishing a code file to identify whether individual cell locations of the memory array are to be fabricated as a first type of cell or as a second type of cell; allocating a first portion of a circuit layout to memory cells of said first type; allocating a second portion of the circuit layout to memory cells of said second type; and, allocating a third portion of the circuit layout to decoder and control logic, the decoder and control logic being shared by the first portion and the second portion.
Claim 2
Independent Claim
101 words
A method for designing a memory array comprising the steps of: establishing a code file to identify whether individual cell locations of the memory array are to be fabricated as a first type of cell or as a second type of cell; allocating a first portion of a circuit layout to memory cells of said first type; allocating a second portion of the circuit layout to memory cells of said second type; and, allocating a third portion of the circuit layout to decoder and control logic, the decoder and control logic being shared by the first portion and the second portion.
Claim 3
Dependent Claim
23 words
A method according to claim 1, wherein the first portion and the second portion are formed as a single array of memory cells.
Claim 4
Dependent Claim
22 words
A method according to claim 1, wherein the decoder and control logic accesses memory cells by addressing the first and second portion.
Claim 5
Dependent Claim
53 words
A method according to claim 1, wherein the step of allocating a second portion further includes a step of redefining memory cells of the first type as memory cells of the second type, the second type representing a memory cell which is of smaller size than a memory cell of the first type.
Claim 6
Dependent Claim
18 words
A method according to claim 1, wherein the first type of memory cells are random access memory cells.
Claim 7
Dependent Claim
18 words
A method according to claim 1, wherein the second type of memory cells are read only memory cells.
Claim 8
Dependent Claim
46 words
A method according to claim 1, wherein the steps of allocating first and second portions each include a step of creating data for storage in said code file for at least one memory cell, the code file identifying characteristics of the at least one memory cell.
Claim 9
Dependent Claim
40 words
A method according to claim 1, wherein the step of allocating a second portion further includes a step of identifying at least one row, one column, or single bit of the first portion as memory cells of the second type.
Claim 10
Independent Claim
77 words
A method of fabricating plural cell locations of a memory array which includes plural types of memory cell structures comprising the steps of: identifying at least two different types of memory cells to be fabricated in the plural cell locations of the memory array; addressing at least one cell location in the memory array with a cell location address that includes a code to identify the type of memory cell to be fabricated in the cell location.
Claim 11
Independent Claim
77 words
A method of fabricating plural cell locations of a memory array which includes plural types of memory cell structures comprising the steps of: identifying at least two different types of memory cells to be fabricated in the plural cell locations of the memory array; addressing at least one cell location in the memory array with a cell location address that includes a code to identify the type of memory cell to be fabricated in the cell location.
Claim 12
Dependent Claim
57 words
A memory device for storing digital information comprising: a memory array including a first type of memory cells and a second type of memory cells; and means for controlling access to the memory cells, the controlling means further including means for addressing a cell location by identifying the type of memory cell which is to be accessed.
Claim 13
Dependent Claim
57 words
A memory device for storing digital information comprising: a memory array including a first type of memory cells and a second type of memory cells; and means for controlling access to the memory cells, the controlling means further including means for addressing a cell location by identifying the type of memory cell which is to be accessed.
Claim 14
Dependent Claim
16 words
Memory device according to claim 10 wherein the memory array is formed on a single substrate.
Claim 15
Dependent Claim
47 words
Memory device according to claim 11, wherein at least one row or column in the memory array of the memory device comprises the first type of memory cells, and at least one other row or column in the memory array comprises the second type of memory cells.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-19 | 1998-03-21 | 1998-09-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-19 | 2002-03-21 | 2002-09-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-19 | 2006-03-21 | 2006-09-20 | $7700.00 | Window Closed / Lapsed |