US5040143A
Expired / Lapsed
US
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Semiconductor memory device
Assignee: Mitsubishi Electric Corp
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Filing: 1990-05-22
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Granted: 1991-08-13
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Expires: 2010-05-22
Abstract
Abstract First and second supply lines are connected to some or all of a plurality of memory cells included in a memory cell array. Only the first supply line is connected to the remaining memory cells. When a voltage of H level is supplied to the first and second supply lines, all memory cells function as SRAM memory cells in which stored information can be rewritten. Meanwhile when H level is applied to the first supply line and L level is applied to the second supply lines, memory cells to which both the first and second supply lines are connected are set to a state in which information of the logic "1" or "0" is fixedly stored. Namely, they function as ROM memory cells. At this time, the remaining member cells to which only the first supply line is connected function as SRAM memory cells. In this manner, by switching the voltages applied to the second supply line, some or all of the memory cell arrays function as SRAM or ROM.
Inventors
- 👤 Tetsuya Matsumura
- 👤 Masahiko Yoshimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 07:31
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C11/005; G11C5/00; G11C5/14; G11C7/00; G11C7/20
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
174 words
A semiconductor memory device having both functions of a static random access memory and of a read only memory, comprising: a plurality of word lines; a plurality of sets of bit line pairs arranged to intersect said plurality of word lines; a plurality of memory cells arranged at intersections of said plurality of word lines and said plurality of sets of bit line pairs; a first supply line connected to each of said plurality of memory cells; a second supply line connected to some or all of said plurality of memory cells; and memory cell selecting means for selecting any of said plurality of memory cells based on an address signal; wherein a memory cell to which both of said first and second supply lines are connected stores information in a writeable manner when a first voltage is applied to said first and second supply lines, and fixedly stores a predetermined information when the first voltage is applied to said first supply line and a second voltage is applied to said second supply line.
Claim 2
Dependent Claim
174 words
A semiconductor memory device having both functions of a static random access memory and of a read only memory, comprising: a plurality of word lines; a plurality of sets of bit line pairs arranged to intersect said plurality of word lines; a plurality of memory cells arranged at intersections of said plurality of word lines and said plurality of sets of bit line pairs; a first supply line connected to each of said plurality of memory cells; a second supply line connected to some or all of said plurality of memory cells; and memory cell selecting means for selecting any of said plurality of memory cells based on an address signal; wherein a memory cell to which both of said first and second supply lines are connected stores information in a writeable manner when a first voltage is applied to said first and second supply lines, and fixedly stores a predetermined information when the first voltage is applied to said first supply line and a second voltage is applied to said second supply line.
Claim 3
Dependent Claim
191 words
A semiconductor memory device according to claim 1, wherein said memory cell to which both of said first and second supply lines are connected comprises: first resistance means having one end connected to one of said first and second supply lines; second resistance means having one end connected to the other one of said first and second supply lines; a first transistor interposed between the other end of said first resistance means and a reference potential source, having its gate connected to the other end of said second resistance means; a second transistor interposed between the other end of said second resistance means and the reference potential source, having its gate connected to the other end of said first resistance means; a third transistor interposed between the other end of said first resistance means and one bit line of a corresponding bit line pair, having its gate connected to corresponding one of said word lines; and a fourth transistor interposed between the other end of said said second resistance means and the other bit line of said corresponding bit line pair, having its gate connected to one of said word lines.
Claim 4
Dependent Claim
41 words
A semiconductor memory device according to claim 2, wherein said first voltage is selected to be sufficiently higher than the potential of said reference potential source, and said second voltage is selected to be approximately equal to the reference potential source.
Claim 5
Dependent Claim
158 words
A semiconductor memory device according to claim 3, wherein said memory cell to which both of said first and second supply lines are connected is divided into a first memory cell in which one end of said first resistance means is connected to said first supply line and one end of said second resistance mans is connected to said second supply line, and a second memory cell in which one end of said first resistance means is connected to said second supply line and one end of said second resistance means is connected to said first supply line; and said first memory cell is set in a state in which information of logic "1" is fixedly stored and said second memory cell is set in a state in which information of logic "0" is fixedly stored, when said first voltage is applied to said first supply line and said second voltage is supplied to said second supply line.
Claim 6
Dependent Claim
57 words
A semiconductor memory device according to claim 1, wherein a memory cell to which only said first supply line out of said first and second supply lines is connected stores information only in a rewritable manner when said first voltage is applied to said first supply line, irrespective of the voltage applied to said second supply line.
References Cited (Backward Citations)
JPS6079597A
Cited
US4964078A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-08-12 | 1995-02-11 | 1995-08-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-08-12 | 1999-02-11 | 1999-08-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-08-12 | 2003-02-11 | 2003-08-13 | $7700.00 | Window Closed / Lapsed |