US4525809A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit
Assignee: NEC Corp
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Filing: 1984-08-27
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Granted: 1985-06-25
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Expires: 2004-08-27
Abstract
Abstract A semiconductor integrated circuit having improved information processing function is disclosed. The integrated circuit comprises a semiconductor substrate, an information processing circuit fabricated on the substrate, a plurality of unit cells each having at least one transistor, a first discretionary wiring for connecting between transistors of the unit cells and a second discretionary wiring for connecting between the information processing circuit and some of the unit cells.
Inventors
- 👤 Fumitaka Chiba
- 👤 Kyozo Shimizu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:40
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907; G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7867; G11; G11C; G11C5/00; G11C5/02; G11C5/025; G11C5/06; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
430 words
An integrated semiconductor circuit comprising a semiconductor substrate having first to fourth edges; a first surface area including a first portion extending along said first edge of said substrate, a second portion extending along said second edge of said substrate, and a third portion extending along said third edge of said substrate; a second surface area having at least first, second and third sides respectively making contact with said first, second and third portions of said first surface area; said first portion of said first surface area lying between said first edge of said substrate and said first side of said second surface area, said second portion of said first surface area lying between said second edge of said substrate and said second side of said second surface area, said third portion of said first surface area lying between said third edge of said substrate and said third side of said second surface area; a computer function block formed on said second surface area of said substrate, said computer function block including in a fixed positional relationship a read only memory on said second surface area, a random access memory on said second surface area, an arithmetic logic unit on said second surface area, a peripheral input/output circuit on said second surface area, a first bus running adjacent to and along said first side of said second surface area, and a second bus running adjacent to and along said third side of said second surface area; each of said random access memory, said arithmetic logic unit and said peripheral input/output circuit having a plurality of wirings arranged in fixed patterns; a first group of logic unit cells formed on said first portion of said first surface area; a second group of logic unit cells formed on said second portion of said first surface area; a third group of logic unit cells formed on said third portion of said first surface area; first discretionary wirings having arbitrary patterns for arbitrarily interconnecting selected ones of said first, second and third groups of logic unit cells to performed arbitrary logic functions; second discretionary wirings having arbitrary patterns for connecting the selected logic unit cells in said first group of logic unit cells to said first bus of said computer function block; and third discretionary wirings having arbitrary patterns for connecting the selected logic unit cells in said third group of logic unit cells to said second bus of said computer function block; whereby said selected logic unit cells form an additional peripheral circuit or an expanded interface circuit for said computer function block.
Claim 2
Dependent Claim
430 words
An integrated semiconductor circuit comprising a semiconductor substrate having first to fourth edges; a first surface area including a first portion extending along said first edge of said substrate, a second portion extending along said second edge of said substrate, and a third portion extending along said third edge of said substrate; a second surface area having at least first, second and third sides respectively making contact with said first, second and third portions of said first surface area; said first portion of said first surface area lying between said first edge of said substrate and said first side of said second surface area, said second portion of said first surface area lying between said second edge of said substrate and said second side of said second surface area, said third portion of said first surface area lying between said third edge of said substrate and said third side of said second surface area; a computer function block formed on said second surface area of said substrate, said computer function block including in a fixed positional relationship a read only memory on said second surface area, a random access memory on said second surface area, an arithmetic logic unit on said second surface area, a peripheral input/output circuit on said second surface area, a first bus running adjacent to and along said first side of said second surface area, and a second bus running adjacent to and along said third side of said second surface area; each of said random access memory, said arithmetic logic unit and said peripheral input/output circuit having a plurality of wirings arranged in fixed patterns; a first group of logic unit cells formed on said first portion of said first surface area; a second group of logic unit cells formed on said second portion of said first surface area; a third group of logic unit cells formed on said third portion of said first surface area; first discretionary wirings having arbitrary patterns for arbitrarily interconnecting selected ones of said first, second and third groups of logic unit cells to performed arbitrary logic functions; second discretionary wirings having arbitrary patterns for connecting the selected logic unit cells in said first group of logic unit cells to said first bus of said computer function block; and third discretionary wirings having arbitrary patterns for connecting the selected logic unit cells in said third group of logic unit cells to said second bus of said computer function block; whereby said selected logic unit cells form an additional peripheral circuit or an expanded interface circuit for said computer function block.
Claim 3
Dependent Claim
32 words
The circuit according to claim 1, in which each of said logic unit cells includes first and second P channel field effect transistors, and first and second N channel field effect transistors.
Claim 4
Dependent Claim
47 words
The circuit according to claim 1, further comprising a plurality of electrode pads formed on said first surface area of said semiconductor substrate and adjacently to said first, second and third edges and a third wiring connected between a selected pad and a selected logic unit cell.
Claim 5
Dependent Claim
355 words
An integrated semiconductor circuit comprising a semiconductor substrate; a memory circuit fabricated on a portion of a surface of said semiconductor substrate; said portion of the surface of said semiconductor substrate having at least three sides; a plurality of logic unit cells fabricated on said semiconductor substrate along said three sides of said portion and arrayed in a matrix of rows and columns, each of said logic unit cells including at least first to sixth internal terminals, first and second field effect transistors of a first conductivity type, third and fourth field effect transistors of a second conductivity type, each of said transistors having a gate, a source, and a drain, one of the drain and source of said first transistor being connected to said first internal terminal; one of the drain and source of said second transistor being connected to said second internal terminal, the others of the drains and sources of said first and second transistors being connected in common to said third internal terminal, one of the drain and source of said third transistor being connected to said fourth internal terminal, one of the drain and a source of said fourth transistor being connected in common to said fifth internal terminal, the others of the drains and sources of said third and fourth transistors being connected in common to said sixth internal terminal, and a first wiring for selectively connecting said internal terminals and at least some gates of said first to fourth transistors within the same logic cell; said first and second transistors of the logic unit cells being arranged in identical columns and disposed in line, said third and fourth transistors of the logic unit cells being arranged in other identical columns and disposed in line, said first and third transistors of the logic unit cells being arranged in identical rows and disposed in lines, said second and fourth transistors of the logic unit cells being arranged in other identical rows and disposed in lines; a second wiring for selectively connecting said logic unit cells; and a third wiring for selectively connecting said memory circuit and said logic unit cells.
Claim 6
Dependent Claim
355 words
An integrated semiconductor circuit comprising a semiconductor substrate; a memory circuit fabricated on a portion of a surface of said semiconductor substrate; said portion of the surface of said semiconductor substrate having at least three sides; a plurality of logic unit cells fabricated on said semiconductor substrate along said three sides of said portion and arrayed in a matrix of rows and columns, each of said logic unit cells including at least first to sixth internal terminals, first and second field effect transistors of a first conductivity type, third and fourth field effect transistors of a second conductivity type, each of said transistors having a gate, a source, and a drain, one of the drain and source of said first transistor being connected to said first internal terminal; one of the drain and source of said second transistor being connected to said second internal terminal, the others of the drains and sources of said first and second transistors being connected in common to said third internal terminal, one of the drain and source of said third transistor being connected to said fourth internal terminal, one of the drain and a source of said fourth transistor being connected in common to said fifth internal terminal, the others of the drains and sources of said third and fourth transistors being connected in common to said sixth internal terminal, and a first wiring for selectively connecting said internal terminals and at least some gates of said first to fourth transistors within the same logic cell; said first and second transistors of the logic unit cells being arranged in identical columns and disposed in line, said third and fourth transistors of the logic unit cells being arranged in other identical columns and disposed in line, said first and third transistors of the logic unit cells being arranged in identical rows and disposed in lines, said second and fourth transistors of the logic unit cells being arranged in other identical rows and disposed in lines; a second wiring for selectively connecting said logic unit cells; and a third wiring for selectively connecting said memory circuit and said logic unit cells.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-06-24 | 1988-12-24 | 1989-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-06-24 | 1992-12-24 | 1993-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-06-24 | 1996-12-24 | 1997-06-25 | $7700.00 | Window Closed / Lapsed |