Patent US5347640A successfully refreshed from Google Patents.
US5347640A
Expired / Lapsed
US
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Circuit for generating addresses for buffering and reading the data from a CD-ROM and method therefor
Assignee: Samsung Electronics Co Ltd
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Filing: 1991-07-18
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Granted: 1994-09-13
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Expires: 2011-07-18
Abstract
Abstract There is disclosed a circuit for improving the efficiency of processing the data of a CD-ROM by partitioning the buffer memory storing the data of the CD-ROM into a number of blocks, which in turn are divided two-dimensionally into X-address axis and Y-address axis so as to specify the blocks by the X- and Y-addresses.
Inventors
- 👤 Ho-Joong You
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 15:20
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0207
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
346 words
A circuit for generating address data for accessing a buffer memory for writing and reading parity data, said circuit comprising: a write address generator for generator write address data in response to a received write control signal and received clock pulses, said write address generator comprising: an initial value generator for generating a first initial value, a second initial value and an initialization control signal, a write control signal generator for generating first clock pulses, second clock pulses, a first load signal and a second load signal in response to said initialization control signal, a first write counter having a first clock input for receiving said first clock pulses, a first load input for receiving said first load signal, and an initialization input for receiving said first initial value, said first write counter being initialized for generating first write address data by counting said first clock pulses up from said first initial value in response to said first load signal, a second write counter having a second clock input for receiving said second clock pulses, a second load input for receiving said second load signal, and an initialization input for receiving said second initial value, said second write counter being initialized for generating second write address data by counting said second clock pulses up from said second initial value in response to said second load signal, and address decoder means for generating a signal for controlling said initial value generator by receiving and decoding said first and second write address data; a read address generator for generating read address data in response to said a read control signal and said received clock pulses; and read/write mode selection means for receiving said first and second write address data, as said write address data generated by said write address generator, for receiving said read address data generated by said read address generator and for selecting one of said write address data and said read address data for output to said buffer memory in response to one of a write mode selection signal and a read mode selection signal.
Claim 2
Dependent Claim
346 words
A circuit for generating address data for accessing a buffer memory for writing and reading parity data, said circuit comprising: a write address generator for generator write address data in response to a received write control signal and received clock pulses, said write address generator comprising: an initial value generator for generating a first initial value, a second initial value and an initialization control signal, a write control signal generator for generating first clock pulses, second clock pulses, a first load signal and a second load signal in response to said initialization control signal, a first write counter having a first clock input for receiving said first clock pulses, a first load input for receiving said first load signal, and an initialization input for receiving said first initial value, said first write counter being initialized for generating first write address data by counting said first clock pulses up from said first initial value in response to said first load signal, a second write counter having a second clock input for receiving said second clock pulses, a second load input for receiving said second load signal, and an initialization input for receiving said second initial value, said second write counter being initialized for generating second write address data by counting said second clock pulses up from said second initial value in response to said second load signal, and address decoder means for generating a signal for controlling said initial value generator by receiving and decoding said first and second write address data; a read address generator for generating read address data in response to said a read control signal and said received clock pulses; and read/write mode selection means for receiving said first and second write address data, as said write address data generated by said write address generator, for receiving said read address data generated by said read address generator and for selecting one of said write address data and said read address data for output to said buffer memory in response to one of a write mode selection signal and a read mode selection signal.
Claim 3
Dependent Claim
194 words
The circuit as claimed in claim 1, said read address generator comprising; a read control signal generator for generating an output code word sequence number, a first clear signal, a second clear signal, first read clock pulses, second read clock pulses, a first read load signal and a second read load signal; a first read counter for generating first read address data by counting said first read clock pulses in response to one of said first clear signal and said first read load signal; a second read counter for generating second read address data by counting said second read clock pulses in response to one of said second clear signal and said second read load signal; an adder for generating summation address data by adding said output code word sequence number and said second read address data; modular operator means for generating a modular address value in response to said summation address data; and selection means for outputting, as said read address data, one of a first output comprised of said first and second read address data and a second output comprised of said modular address value and said output code word sequence number.
Claim 4
Dependent Claim
60 words
The circuit as claimed in claim 1, further comprised of said read/write selection means comprising: a first three-state buffer for outputting said write address data to said buffer memory in response to said write mode selection signal; and a second three-state buffer for outputting said read address data to said buffer memory in response to said read mode selection signal.
Claim 5
Dependent Claim
302 words
A circuit for generating address data for accessing a buffer memory for writing and reading parity data, said circuit comprising: a write address generator for generating write address data in response to a received write control signal and received clock pulses; a read address generator for generating read address data in response to said a read control signal and said received clock pulses, said read address generator comprising: a read control signal generator for generating an output code word sequence number, a first clear signal, a second clear signal, first read clock pulses, second read clock pulses, a first read load signal and a second read load signal, a first read counter for generating first read address data by counting said first read clock pulses in response to one of said first clear signal and said first read load signal, a second read counter for generating second read address data by counting said second read clock pulses in response to one of said second clear signal and said second read load signal, an adder for generating summation address data by adding said output code word sequence number and said second read address data, modular operator means for generating a modular address value in response to said summation address data, and selection means for outputting, as said read address data, said first and second read address data or said modular address value and said output code word sequence number; and read/write mode selection means for receiving said write address data generated by said write address generator and said read address data generated by said read address generator and for selecting one of said write address data and said read address data for output to said buffer memory in response to one of a write mode selection signal and a read mode selection signal.
Claim 6
Dependent Claim
302 words
A circuit for generating address data for accessing a buffer memory for writing and reading parity data, said circuit comprising: a write address generator for generating write address data in response to a received write control signal and received clock pulses; a read address generator for generating read address data in response to said a read control signal and said received clock pulses, said read address generator comprising: a read control signal generator for generating an output code word sequence number, a first clear signal, a second clear signal, first read clock pulses, second read clock pulses, a first read load signal and a second read load signal, a first read counter for generating first read address data by counting said first read clock pulses in response to one of said first clear signal and said first read load signal, a second read counter for generating second read address data by counting said second read clock pulses in response to one of said second clear signal and said second read load signal, an adder for generating summation address data by adding said output code word sequence number and said second read address data, modular operator means for generating a modular address value in response to said summation address data, and selection means for outputting, as said read address data, said first and second read address data or said modular address value and said output code word sequence number; and read/write mode selection means for receiving said write address data generated by said write address generator and said read address data generated by said read address generator and for selecting one of said write address data and said read address data for output to said buffer memory in response to one of a write mode selection signal and a read mode selection signal.
Claim 7
Dependent Claim
219 words
The circuit as claimed in claim 4, said write address generator comprising: an initial value generator for generating a first initial value, a second initial value and an initialization control signal; a write control signal generator for generating first clock pulses, second clock pulses, a first load signal and a second load signal in response to said initialization control signal; a first write counter having a first clock input for receiving said first clock pulses, a first load input for receiving said first load signal, and an initialization input for receiving said first initial value, said first write counter for generating first write address data by being initialized for counting said first clock pulses up from said first initial value in response to said first load signal; a second write counter having a second clock input for receiving said second clock pulses, a second load input for receiving said second load signal, and an initialization input for receiving said second initial value, said second write counter for generating second write address data by being initialized for counting said second clock pulses up from said second initial value in response to said second load signal; and address decoder means for controlling said initial value generator by receiving and decoding said first and second write address data for generating a signal.
Claim 8
Dependent Claim
57 words
The circuit as claimed in claim 4, said read/write selection means comprising: a first three-state buffer for outputting said write address data to said buffer memory in response to said write mode selection signal; and a second three-state buffer for outputting said read address data to said buffer memory in response to said read mode selection signal.
Claim 9
Dependent Claim
251 words
A circuit for generating first and second write address data for accessing a buffer memory of a CD-ROM for writing P-parity data and Q-parity data, said circuit comprising: an initial value generator for generating a first initial value, a second initial value and an initialization control signal; a write control signal generator for receiving a timing signal comprised of command data, for processing said command data for generating first clock pulses, second clock pulses, a first load signal and a second load signal in response to said initialization control signal; a first write counter having a first clock input for receiving said first clock pulses, a first load input for receiving said first load signal, and an initialization input for receiving said first initial value, said first write counter for generating said first write address data by being initialized for counting said first clock pulses up from said first initial value in response to said first load signal; a second write counter having a second clock input for receiving said second clock pulses, a second load input for receiving said second load signal, and an initialization input for receiving said second initial value, said second write counter for generating said second write address data by being initialized for counting said second clock pulses up from said second initial value in response to said second load signal; and address decoder means for generating a signal for controlling said initial value generator by receiving and decoding said first and second write address data.
Claim 10
Dependent Claim
251 words
A circuit for generating first and second write address data for accessing a buffer memory of a CD-ROM for writing P-parity data and Q-parity data, said circuit comprising: an initial value generator for generating a first initial value, a second initial value and an initialization control signal; a write control signal generator for receiving a timing signal comprised of command data, for processing said command data for generating first clock pulses, second clock pulses, a first load signal and a second load signal in response to said initialization control signal; a first write counter having a first clock input for receiving said first clock pulses, a first load input for receiving said first load signal, and an initialization input for receiving said first initial value, said first write counter for generating said first write address data by being initialized for counting said first clock pulses up from said first initial value in response to said first load signal; a second write counter having a second clock input for receiving said second clock pulses, a second load input for receiving said second load signal, and an initialization input for receiving said second initial value, said second write counter for generating said second write address data by being initialized for counting said second clock pulses up from said second initial value in response to said second load signal; and address decoder means for generating a signal for controlling said initial value generator by receiving and decoding said first and second write address data.
Claim 11
Dependent Claim
31 words
The circuit as claimed in claim 7, further comprised of a tri-state buffer responsive to a write mode signal for receiving and supplying said write address data to said buffer memory.
Claim 12
Dependent Claim
211 words
A circuit for generating address data for accessing a buffer memory of a CD-ROM for reading P-parity data and Q-parity data, said circuit comprising: a read control signal generator for receiving a timing signal comprised of command data, for processing said command data for generating a code word sequence number, a first clear signal, a second clear signal, first read clock pulses, second read clock pulses, a first read load signal and a second read load signal; a first read counter for generating first read address data by counting said first read clock pulses in response to one of said first clear signal and said first read load signal; a second read counter for generating second read address data by counting said second read clock pulses in response to one of said second clear signal and said second read load signal; an adder for generating summation address data by adding said output code word sequence number and said second read address data; modular operator means for generating a modular address value in response to said summation address data; and selection means for outputting, as said address data for accessing said buffer memory, said first and second read address data or said modular address value and said output code word sequence number.
Claim 13
Dependent Claim
211 words
A circuit for generating address data for accessing a buffer memory of a CD-ROM for reading P-parity data and Q-parity data, said circuit comprising: a read control signal generator for receiving a timing signal comprised of command data, for processing said command data for generating a code word sequence number, a first clear signal, a second clear signal, first read clock pulses, second read clock pulses, a first read load signal and a second read load signal; a first read counter for generating first read address data by counting said first read clock pulses in response to one of said first clear signal and said first read load signal; a second read counter for generating second read address data by counting said second read clock pulses in response to one of said second clear signal and said second read load signal; an adder for generating summation address data by adding said output code word sequence number and said second read address data; modular operator means for generating a modular address value in response to said summation address data; and selection means for outputting, as said address data for accessing said buffer memory, said first and second read address data or said modular address value and said output code word sequence number.
Claim 14
Dependent Claim
30 words
The circuit as claimed in claim 9, further comprised of a tri-state buffer responsive to a read mode signal for receiving and supplying said address data to said buffer memory.
Claim 15
Independent Claim
180 words
A method for accessing a buffer memory of a CD-ROM said method comprising the steps of: generating first and second write address data for writing P-parity data and Q-parity data to said buffer memory, said generating step comprising the steps of; generating first and second initial values and an initializing signal in response to a initializing control signal, processing write command data of a timing signal for generating first and second clock pulses, and for generating first and second load signals in response to said initializing signal, loading said first initial value into a first counter in response to said first load signal and counting said first clock pulses up to a first count from said initial value, said first count forming said first write address data, loading said second initial value into a second counter in response to said second load signal and counting said second clock pulses up to a second count from said initial value, said second count forming said second write address data, and decoding said first and second counts for generating said initializing control signal.
Claim 16
Independent Claim
180 words
A method for accessing a buffer memory of a CD-ROM said method comprising the steps of: generating first and second write address data for writing P-parity data and Q-parity data to said buffer memory, said generating step comprising the steps of; generating first and second initial values and an initializing signal in response to a initializing control signal, processing write command data of a timing signal for generating first and second clock pulses, and for generating first and second load signals in response to said initializing signal, loading said first initial value into a first counter in response to said first load signal and counting said first clock pulses up to a first count from said initial value, said first count forming said first write address data, loading said second initial value into a second counter in response to said second load signal and counting said second clock pulses up to a second count from said initial value, said second count forming said second write address data, and decoding said first and second counts for generating said initializing control signal.
Claim 17
Dependent Claim
67 words
The method as claimed in claim 11 further comprising the step of: supplying block point data, plane point data, said first write address data and said second write address data to a tri-state buffer for output to said buffer memory as a write address signal for writing one of said P and Q parity data to said buffer memory in response to a write mode selection signal,
Claim 18
Dependent Claim
157 words
The method as claimed in claim 11, further comprising the steps of: generating read address signals for reading P-parity data and Q-parity data from said buffer memory, said read address signal generating step comprising the steps of; processing read command data of said timing signal for generating a code word sequence number, for generating first and second read clock pulses, for generating first and second read load signal and for generating first and second clear signals, supplying said first clear signals, said first read load signals and said first read clock pulses to a first read counter, supplying said second clear signals, said second read load signals and said second read clock pulses to a second read counter, counting said first read clock pulses to generate first read address data, counting said second read clock pulses to generate second read address data, and outputting said first and second read address data in response to a selection signal.
Claim 19
Dependent Claim
67 words
The method as claimed in claim 13, further comprising the step of: supplying block point data, plane point data, said first read address data and said second read address data to a tri-state buffer for output to said buffer memory as a read address signal for reading one of said P and Q parity data from said buffer memory in response to a read mode selection signal.
Claim 20
Independent Claim
244 words
A method for accessing a buffer memory of a CD-ROM said method comprising the steps of: generating read address signals for reading P-parity data and Q-parity data from said buffer memory, said read address signal generating step comprising the steps of; processing read command data of a timing signal for generating a code word sequence number, for generating first and second clock pulses, for generating first and second load signals and for generating first and second clear signals, supplying said first clear signals, said first load signals and said first clock pulses to a first counter, supplying said second clear signals, said second load signals and said second clock pulses to a second counter, counting said first clock pulses to generate first read address data, counting said second block pulses to generate second read address data, adding said code word sequence number and said second read address data for generating summation data, applying a modular value to said summation data for generating third read address data, supplying said first and third read address data to a first selection means, supplying said code word sequence number and said second read address data to a second selection means, and controlling said first and second selection means for selectively outputting one of a first output comprised of said first and second read address data and a second output comprised of said third read address data and said code word sequence number, in response to a selection signal.
Claim 21
Independent Claim
244 words
A method for accessing a buffer memory of a CD-ROM said method comprising the steps of: generating read address signals for reading P-parity data and Q-parity data from said buffer memory, said read address signal generating step comprising the steps of; processing read command data of a timing signal for generating a code word sequence number, for generating first and second clock pulses, for generating first and second load signals and for generating first and second clear signals, supplying said first clear signals, said first load signals and said first clock pulses to a first counter, supplying said second clear signals, said second load signals and said second clock pulses to a second counter, counting said first clock pulses to generate first read address data, counting said second block pulses to generate second read address data, adding said code word sequence number and said second read address data for generating summation data, applying a modular value to said summation data for generating third read address data, supplying said first and third read address data to a first selection means, supplying said code word sequence number and said second read address data to a second selection means, and controlling said first and second selection means for selectively outputting one of a first output comprised of said first and second read address data and a second output comprised of said third read address data and said code word sequence number, in response to a selection signal.
Claim 22
Dependent Claim
67 words
The method as claimed in claim 15, further comprising the step of: supplying block point data, plane point data, said first read address data and said second read address data to a tri-state buffer for output to said buffer memory as a read address signal for reading one of said P and Q parity data from said buffer memory in response to a read mode selection signal.
Claim 23
Dependent Claim
67 words
The method as claimed in claim 15, further comprising the step of: supplying block point data, plane point data, said code word sequence number and said third read address data to a tri-state buffer for output to said buffer memory as a read address signal for reading one of said P and Q parity data from said buffer memory in response to a read mode selection signal.
Claim 24
Dependent Claim
190 words
The method as claimed in claim 15, further comprising the steps of: generating first and second write address data for writing P-parity data and Q-parity data to said buffer memory, said first and second write address data generating step comprising the steps of; generating first and second initial values and an initializing signal in response to a initializing control signal, processing write command data of said timing signal for generating first and second write clock pulses, and for generating first and second write load signals in response to said initializing signal, loading said first initial value into a first write counter in response to said first write load signal and counting said first write clock pulses up to a first count from said initial value, said first count forming said first writing address data, loading said second initial value into a second write counter in response to said second write load signal and counting said second write clock pulses up to a second count from said initial value, said second count forming said second write address data, and decoding said first and second counts for generating said initializing control signal.
Claim 25
Dependent Claim
67 words
The method as claimed in claim 18, further comprising the steps of: supplying block point data, plane point data, said first write address data and said second write address data to a tri-state buffer for output to said buffer memory as a write address signal for writing one of said P and Q parity data to said buffer memory in response to a write mode selection signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-12 | 1998-03-14 | 1998-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-12 | 2002-03-14 | 2002-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-12 | 2006-03-14 | 2006-09-13 | $7700.00 | Window Closed / Lapsed |