Abstract An address generating circuit (13) generates a reading address for reading a buffer memory (16) so that so-called P and Q codes for a CD-ROM which have parameters i and j can be decoded. The reading address is obtainable based on a formula RDA=H+2L+p, where H is a starting address of one block not inluding synchronous signal or pattern, L is a symbolic location of a symbol, and p is a sign for designating that the symbol is included in a LSB byte plane or an MSB byte plane. A first full adder (25) generates the symbolic location L based on the parameter i and j with various constants being given from a constant generator (23) so as to give the symbolic location L to a second full adder (21). The starting address H is given from a writing address pointer (12a). The second full adder adds H, 2L and p to apply the reading address to an address bus. In addition, the symbolic location L is latched in a symbol off-set address (26) and, if necessary, fed-back to the first full adder through multiplexers (24, 27) when the next symbolic location is to be generated.
An address generating circuit which generates reading addresses for addressing a memory in which a plurality of error correcting code words composed of data and parity symbols for detecting or correcting errors in the data are sequentially stored for each symbol so that said data and parity symbols are sequentially read from said memory for each symbol in an order corresponding to a decoding order number so as to decode said error correcting code words, said error correcting code words being formed by data arranged for each symbol in a predetermined arrangement and parity symbols which are added to the data based on said predetermined arrangement, comprising: a first operation circuit for generating a symbolic location of each symbol in said predetermined arrangement based on at least the order number of the symbol of said error correcting code words; and a second operation circuit for generating an address of each symbol with respect to said memory based on at least said symbolic location being outputted from said first operation circuit.
Claim 2
Dependent Claim
170 words
An address generating circuit which generates reading addresses for addressing a memory in which a plurality of error correcting code words composed of data and parity symbols for detecting or correcting errors in the data are sequentially stored for each symbol so that said data and parity symbols are sequentially read from said memory for each symbol in an order corresponding to a decoding order number so as to decode said error correcting code words, said error correcting code words being formed by data arranged for each symbol in a predetermined arrangement and parity symbols which are added to the data based on said predetermined arrangement, comprising: a first operation circuit for generating a symbolic location of each symbol in said predetermined arrangement based on at least the order number of the symbol of said error correcting code words; and a second operation circuit for generating an address of each symbol with respect to said memory based on at least said symbolic location being outputted from said first operation circuit.
Claim 3
Dependent Claim
54 words
An address generating circuit in accordance with claim 1, wherein said first operation circuit generates the symbolic location of the each symbol in said predetermined arrangement on the basis of the order number of the error correcting code words as well as the order number of the symbol of the error correcting code word.
Claim 4
Dependent Claim
34 words
An address generating circuit in accordance with claim 2, wherein said first operation circuit includes a feed-back loop responsive to the symbolic location being outputted for generating a symbolic location of a subsequent symbol.
Claim 5
Dependent Claim
28 words
An address generating circuit in accordance with claim 3, wherein said first operation circuit includes a constant generation circuit for generating a constant based on said predetermined arrangement.