Address generator with variable scan patterns

Claim 2

An address generator for scanning a first addressable memory logically configures in a rectangular matrix wherein a pattern of data is stored in a predetermined orientation with respect to said matrix, and for writing to a second addressable memory comprising: input means for receiving parameters from an external source, said parameters being programmable for providing a predetermined scan pattern from a plurality of scan patterns substantially independent of said predetermined orientation, processor means coupled to receive said parameters for computing angles of an envelope defining the contour of a scan pattern and angles of rotation for successive lines of said scan pattern. read address generator means responsive to said processor means for selectively generating address signals so as to read out said pattern information in a given direction with respect to said predetermined orientation, wherein said given direction is substantially independent of said predetermined orientation, and for providing incremental horizontal and vertical values of read addresses for generating each line of said scan pattern and reading values of digital signals stored in said first memory at corresponding addresses, write address generator means coupled to receive said parameters in the form of a first parameter defining a starting point of a first scan line, a second parameter defining the slope of said scan line, and a third parameter defining the slope of starting points of successive scan line, said first, second, and third parameters being dynamically and sequentially variable in accordance with command signals from said external source to form one of said plurality of scan patterns, for generating sequential write addresses for writing into said second addressable memory configured in a rectangular matrix, counter means for counting the number of incremental addresses in accordance with a predetermined line length and the number of scan lines in accordance with a predetermined line count and for providing a signal indicative of the completion of a scan line and a signal indicative of the generation of a complete frame at the completion of said line count, and timing means for generating timing and sequencing signals for generating each scan line, reading said first addressable memory along said scan lines, and writing the contents of said addressable memory into said second addressable memory.

Claim 3

An address generator as set forth in claim 1, wherein said parameters applied to said processor means comprise the corner points of a geometric figure.

Claim 4

An address generator as set forth in claim 2, wherein said geometric figure comprises a trapezoid.

Claim 5

An address generator as set forth in claim 3, wherein said scanning line shave a slope of zero with respect to a horizontal axis of said rectangular matrix and the slope with respect to said horizontal axis of an edge of said trapezoid defined by said envelope determines the start or end points of successive scan lines.

Claim 6

An address generator as set forth in claim 4, wherein said geometric figure comprises a rectangle.

Claim 7

An address generator as set forth in claim 5, wherein successive scan lines are scanned in parallel fashion with respect to one another, but not necessarily parallel to an axis of said rectangular matrix, and the slope of an edge of said rectangle defines the start or end points of successive scan lines.

Claim 8

An address generator as set forth in claim 2, wherein said geometric figure comprises at least a portion of a star having a plurality of radially extending members, and said input parameters comprise a center point, a line radius, and an included angle or a start angle and a stop angle defining an included angle.

Claim 9

An address generator as set forth in claim 2, wherein said processor means comprises trigonometric look-up tables responsive to address parameters for generating values of slopes of said angles in Cartesian coordinate form.

Claim 10

An address generator for scanning a first addressable memory logically configures in a rectangular matrix and writing to a second addressable memory comprising: input means for receiving parameters from an external source, said parameters being programmable for providing a predetermined scan pattern, processor means coupled to receive said parameters for computing angles of an envelope defining the contour of a scan pattern and angles of rotation for successive lines of said scan pattern, read address generator means responsive to said processor means for providing incremental horizontal and vertical values of read addresses for generating each line of said scan pattern and reading values of digital signals stored in said first memory at corresponding addresses, write address generator means coupled to receive said scan pattern for generating sequential write addresses for writing into said second addressable memory configures in a rectangular matrix, counter means for counting the number of incremental addresses in accordance with a predetermined line length and the number of scan lines in accordance with a predetermined line count and for providing a signal indicative of the completion of a scan line and a signal indicative of the generation of a completed frame at the completion of said line count, and timing means for generating timing and sequencing signals for generating each scan line, reading said first addressable memory along said scan lines, and writing the con tents of said first addressable memory into said second addressable memory; wherein said read address generator means comprises: an X read address generator and a Y read address generator for receiving parameters representative of the starting address of a scan line, first incremental X and Y correction values corresponding to a slope of said scan line, and second incremental X and Y correction values corresponding to the relative slope of successive scan lines, means for computing read addresses corresponding to at least one of said scan lines by summing the respective X and Y starting addresses and corresponding first X and Y incremental values and sequentially incrementing said summed read addresses by said first incremental values, means responsive to the completion of a scan line for summing the respective X and Y starting points and corresponding second X and Y incremental values, thereby defining the start of a successive scan line, and means for sequentially incrementing said read address by summing said first and second X and Y incremental values therewith until a predetermined plurality of scan lines defining a frame is completed.

Claim 11

An address generator for scanning a first addressable memory logically configures in a rectangular matrix and writing to a second addressable memory comprising: input means for receiving parameters from an external source, said parameters being programmable for providing a predetermined scan pattern, processor means coupled to receive said parameters for computing angles of an envelope defining the contour of a scan pattern and angles of rotation for successive lines of said scan pattern, read address generator means responsive to said processor means for providing incremental horizontal and vertical values of read addresses for generating each line of said scan pattern and reading values of digital signals stored in said first memory at corresponding addresses, write address generator means coupled to receive said scan pattern for generating sequential write addresses for writing into said second addressable memory configures in a rectangular matrix, counter means for counting the number of incremental addresses in accordance with a predetermined line length and the number of scan lines in accordance with a predetermined line count and for providing a signal indicative of the completion of a scan line and a signal indicative of the generation of a completed frame at the completion of said line count, and timing means for generating timing and sequencing signals for generating each scan line, reading said first addressable memory along said scan lines, and writing the con tents of said first addressable memory into said second addressable memory; wherein said read address generator means comprises: an X read address generator and a Y read address generator for receiving parameters representative of the starting address of a scan line, first incremental X and Y correction values corresponding to a slope of said scan line, and second incremental X and Y correction values corresponding to the relative slope of successive scan lines, means for computing read addresses corresponding to at least one of said scan lines by summing the respective X and Y starting addresses and corresponding first X and Y incremental values and sequentially incrementing said summed read addresses by said first incremental values, means responsive to the completion of a scan line for summing the respective X and Y starting points and corresponding second X and Y incremental values, thereby defining the start of a successive scan line, and means for sequentially incrementing said read address by summing said first and second X and Y incremental values therewith until a predetermined plurality of scan lines defining a frame is completed.

Claim 12

An address generator as set forth in claim 9, further comprising: means for sequentially addressing a plurality of storage location of said first addressable memory of the form P1=X,Y, P2=X+1,Y, P3=X,Y+1, P4=X+1, Y+1, said points neighboring a point corresponding to the value of a storage location in said first addressable memory.

Claim 13

A counter means as set forth in claim 9, comprising: latch means for receiving and storing an initial X count corresponding to said line length from said input means, said latch means also responsive to a control signal from said input means to return or decrement said initial count, first presettable counter means responsive to said input means to be preset to said initial X count and responsive to said latch means for providing a decremented X count, first logic means coupled to said first presettable counter means to detect when a predetermined X count has been reached thereby and to provide a signal denoting completion of a scan line and for resetting the count of said first counter means to a further initial X count at a successive scan line, second presettable counter means responsive to said input means to be preset to an initial Y count corresponding to the number of scan lines in a frame and further responsive to said input means for providing a decremented Y count, and second logic means coupled to said second counter means to detect when a predetermined Y count has been reached, thereby to provide a signal denoting reading of a complete frame for writing the contents of said further addressable memory means into said display means.

Claim 14

A write address generator as set forth in claim 9, further comprising: means coupled to said timing means for receiving regular clock pulses, address counting means for counting said clock pulses to produce an address for said second addressable memory, means for supplying said address to said second addressable memory to designate an address corresponding to a storage location therein in which stored data is written, and means coupled to said timing means for selectively enabling said means for supplying an address.

Claim 15

A write address generator as set forth in claim 12, further comprising mean for writing the contents of said second addressable memory into a display means.