Patent US5346834A successfully refreshed from Google Patents.
US5346834A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for manufacturing a semiconductor device and a semiconductor memory device
Assignee: Renesas Electronics Corp
•
Filing: 1992-03-03
•
Granted: 1994-09-13
•
Expires: 2012-03-03
Abstract
Abstract An improved method for manufacturing an insulated gate field effect transistor is provided. As a first step, a silicon oxide film is grown on a silicon substrate, and a first silicon nitride film is deposited thereon. The first silicon nitrite film, the silicon oxide film and the silicon substrate are then etched using a resist pattern as a mask to form a silicon island which includes at least a part of the silicon substrate. A second silicon oxide film is then grown on the surface of the silicon substrate exposed by the second step, as well as on the surface of the silicon island, and a second silicon nitrite film is deposited thereon. The second silicon nitrite film is then etched to leave a portion of the second silicon nitrite film deposited on a side wall of the silicon island. After this, a third silicon oxide film is grown by thermal oxidation of the surface of the silicon substrate to electrically separate the silicon island from the silicon substrate. Next a gate electrode is formed on silicon island, followed by forming source and drain regions in the silicon island employing the gate electrode as a mask.
Inventors
- 👤 Dai Hisamoto
- 👤 Toru Kaga
- 👤 Shinichiro Kimura
- 👤 Masahiro Moniwa
- 👤 Haruhiko Tanaka
- 👤 Atsushi Hiraiwa
- 👤 Eiji Takeda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:39
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/62; H10B; H10B10/00; H10B10/12; H10B10/125; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/05; H10B12/30; H10B12/31; H10D30/01; H10D30/021; H10D30/024; H10D30/031; H10D30/0321; H10D30/0323; H10D30/67; H10D30/6729; H10D30/673; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6744; H10D44/00; H10D44/01; H10D44/041; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/335; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/02; H10D84/03; H10D84/038; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/061; H10W10/10; H10W10/181; H10P90/1912; Y; Y10; Y10S; Y10S148/00; Y10S148/014
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
285 words
A method of manufacturing a semiconductor memory device comprising: a first step of forming a trench in a surface silicon substrate and forming an insulating film on an inner wall of said trench up to a predetermined height; a second step of packing a conductor layer into said trench up to the surface level of said silicon substrate; a third step of growing a first silicon oxide film on said silicon substrate and on said conductor layer and depositing a first silicon nitride film thereon; a fourth step of etching said first silicon nitride film, said first silicon oxide film, said silicon substrate and said conductor layer at least to the level of said predetermined height by employing a resist pattern as a mask to form a silicon island comprised of a part of said silicon substrate and a part of said conductor layer; a fifth step of growing a second silicon oxide film on a surface of said silicon substrate exposed by said second step and on a surface of said silicon island, depositing a second silicon nitride film thereon, and etching said second silicon nitride film so as to leave a portion of said second silicon nitride film deposited on a side wall of said silicon island and deposited on a connection of said silicon island and said conductor layer, a sixth step of growing a third silicon oxide film by thermal oxidation of the surface of said silicon substrate to separate electrically said silicon island from said silicon substrate; and a seventh step of forming a gate electrode on said silicon island and forming a source region and drain region in said silicon island by employing said gate electrode as a mask.
Claim 2
Independent Claim
285 words
A method of manufacturing a semiconductor memory device comprising: a first step of forming a trench in a surface silicon substrate and forming an insulating film on an inner wall of said trench up to a predetermined height; a second step of packing a conductor layer into said trench up to the surface level of said silicon substrate; a third step of growing a first silicon oxide film on said silicon substrate and on said conductor layer and depositing a first silicon nitride film thereon; a fourth step of etching said first silicon nitride film, said first silicon oxide film, said silicon substrate and said conductor layer at least to the level of said predetermined height by employing a resist pattern as a mask to form a silicon island comprised of a part of said silicon substrate and a part of said conductor layer; a fifth step of growing a second silicon oxide film on a surface of said silicon substrate exposed by said second step and on a surface of said silicon island, depositing a second silicon nitride film thereon, and etching said second silicon nitride film so as to leave a portion of said second silicon nitride film deposited on a side wall of said silicon island and deposited on a connection of said silicon island and said conductor layer, a sixth step of growing a third silicon oxide film by thermal oxidation of the surface of said silicon substrate to separate electrically said silicon island from said silicon substrate; and a seventh step of forming a gate electrode on said silicon island and forming a source region and drain region in said silicon island by employing said gate electrode as a mask.
References Cited (Backward Citations)
US5026658A
Cited
US4830978A
Cited
US5183774A
Cited
US5100823A
Cited
US5102819A
Cited
US5075248A
Cited
US5182224A
Cited
US5185284A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-12 | 1998-03-14 | 1998-09-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-12 | 2002-03-14 | 2002-09-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-12 | 2006-03-14 | 2006-09-13 | $7700.00 | Window Closed / Lapsed |