US5026658A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making a trench capacitor dram cell
Assignee: Panasonic Holdings Corp
•
Filing: 1989-09-08
•
Granted: 1991-06-25
•
Expires: 2009-09-08
Abstract
Abstract Disclosed is a semiconductor memory device (DRAM) which includes a plurality of island regions, at least one cell transistor disposed on each island region and cylindrical capacitor surrounding said each island region. By so composing, the capacity of the cell capacitor incorporated into a small space can be increased. Also disclosed is method of fabricating a semiconductor memory device which includes a step of forming a groove having a necessary depth in a semiconductor substrate, a step of depositing a membrane excelling in coverage on it, a step of etching by an etching method having a strong anisotropy in the vertical direction while leaving said deposit membrane on sidewall, and a step of etching deeper the exposed portion of the semiconductor surface in the groove and forming capacity element and isolation region by using this deep trench.
Inventors
- 👤 Genshu Fuse
- 👤 Toshio Yamada
- 👤 Shinji Odanaka
- 👤 Masaki Fukumoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 05:18
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/66; H10D1/665; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/33; H10B12/37; H10B12/373
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
250 words
A method of fabricating a semiconductor memory device comprising: forming a first groove in a semiconductor substrate of a predetermined conductivity type, the side of the first groove defined by a sidewall of the substrate and the bottom of the first groove defined by a bottom wall of the substrate; selectively forming, in the semiconductor substrate, a region of said predetermined conductivity type and a region of conductivity type opposite to said predetermined conductivity type by doping the sidewall defining said first groove with impurity using an ion-implantation technique; depositing a film in said first groove; etching the deposited film using an etching process having a strong anisotropy as measured in the vertical direction so as to expose said bottom wall of the substrate and leave the deposited film only on the sidewall of the substrate defining said first groove; etching the semiconductor substrate at the exposed bottom wall thereof to form a second groove in the semiconductor substrate which extends from the bottom of said first groove to a location disposed within said substrate at which the bottom of said second groove is defined; forming a capacitor of the memory device by forming a first electrode connected to said region of opposite conductivity type, a capacitor insulation layer, and a second electrode in said second groove; burying an insulating layer for isolation in said first groove; and forming an MOS transistor having a source or drain region of another conductivity type defined in a portion of said semiconductor substrate.
Claim 2
Independent Claim
250 words
A method of fabricating a semiconductor memory device comprising: forming a first groove in a semiconductor substrate of a predetermined conductivity type, the side of the first groove defined by a sidewall of the substrate and the bottom of the first groove defined by a bottom wall of the substrate; selectively forming, in the semiconductor substrate, a region of said predetermined conductivity type and a region of conductivity type opposite to said predetermined conductivity type by doping the sidewall defining said first groove with impurity using an ion-implantation technique; depositing a film in said first groove; etching the deposited film using an etching process having a strong anisotropy as measured in the vertical direction so as to expose said bottom wall of the substrate and leave the deposited film only on the sidewall of the substrate defining said first groove; etching the semiconductor substrate at the exposed bottom wall thereof to form a second groove in the semiconductor substrate which extends from the bottom of said first groove to a location disposed within said substrate at which the bottom of said second groove is defined; forming a capacitor of the memory device by forming a first electrode connected to said region of opposite conductivity type, a capacitor insulation layer, and a second electrode in said second groove; burying an insulating layer for isolation in said first groove; and forming an MOS transistor having a source or drain region of another conductivity type defined in a portion of said semiconductor substrate.
Claim 3
Dependent Claim
34 words
The method of fabricating a semiconductor memory device as claimed in claim 1, wherein the depositing of the film comprises depositing an insulating film in said first groove using a reduced pressure CVD process.
Claim 4
Dependent Claim
46 words
The method of fabricating a semiconductor memory device as claimed of claim 1, wherein the forming of the first electrode of the capacitor comprises using an ion-implantation technique to form the first electrode on a sidewall of the substrate defining the side of said second groove.
Claim 5
Dependent Claim
44 words
The method of fabricating a semiconductor memory device as claimed of claim 1, and further comprising doping the semiconductor substrate at said location with an impurity of a conductivity type that is the same as that of the substrate to form an isolation region.
Claim 6
Dependent Claim
57 words
The method of fabricating a semiconductor memory device as claimed of claim 1, wherein the forming of the first groove comprises forming the first groove so as to surround a transistor region where said MOS transistor is formed, and the etching of the semiconductor substrate forms said second groove around a lower portion of said transistor region.
Claim 7
Dependent Claim
33 words
The method of fabricating a semiconductor memory device as claimed of claim 1, wherein the forming of the second electrode of said capacitor comprises forming a second electrode polysilicon in said second groove.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-24 | 1994-12-24 | 1995-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-24 | 1998-12-24 | 1999-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-24 | 2002-12-24 | 2003-06-25 | $7700.00 | Window Closed / Lapsed |