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US5343439A
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Memory apparatus
Assignee: NEC Corp
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Filing: 1991-10-18
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Granted: 1994-08-30
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Expires: 2011-10-18
Abstract
Abstract A memory apparatus includes a memory cell array for storing a data, a shift register for receiving an input serial data to be stored in the memory cell array and supplying an output serial data to be read from the memory cell array, and a transfer gate for transferring a data in parallel between the shift register and the memory cell array. In the shift register, the input serial data is shifted to an output side thereof until the first bit reaches to the final step thereof. Then, the input serial data is transferred to be stored in the memory cell array by the transfer gate. Thus, when the stored data is read therefrom, no invalid bit is supplied even at the beginning time even if the shift register is longer than the input serial data.
Inventors
- 👤 Yasuharu Hoshino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 23:41
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1072; G11C11/00; G11C11/21; G11C11/34; G11C11/40
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
134 words
A memory apparatus comprising: a memory cell array for storing a data of bits; a shift register for receiving an input serial data to be stored in said memory cell array and supplying an output serial data to be read from said memory cell array; a transfer gate which is positioned between said memory cell array and said shift register to transfer said data of bits in parallel therebetween; and a control circuit for controlling said shift register to shift said input serial data; wherein said control circuit controls said shift register to shift said input serial data until a first bit thereof reaches to a final step of said shift register, and then controls said transfer gate to transfer said input serial data in parallel to be stored in said memory cell array.
Claim 2
Dependent Claim
134 words
A memory apparatus comprising: a memory cell array for storing a data of bits; a shift register for receiving an input serial data to be stored in said memory cell array and supplying an output serial data to be read from said memory cell array; a transfer gate which is positioned between said memory cell array and said shift register to transfer said data of bits in parallel therebetween; and a control circuit for controlling said shift register to shift said input serial data; wherein said control circuit controls said shift register to shift said input serial data until a first bit thereof reaches to a final step of said shift register, and then controls said transfer gate to transfer said input serial data in parallel to be stored in said memory cell array.
Claim 3
Dependent Claim
118 words
A memory apparatus, according to claim 1, wherein: said control circuit comprises: a counter for counting clock signals; a control signal generating circuit for generating control signals to be supplied to said memory array, said shift register, said transfer gate, and said counter; and a comparator for comparing the number of total steps of said shift register and a counted value of said counter to supply an equal signal to be supplied to said control signal generating circuit, when said counted value becomes equal to said number of total steps, said counter starting a count of said clock signals, when said first bit of said input serial data is stored in a first step of said shift register.
Claim 4
Dependent Claim
47 words
A memory apparatus, according to claim 1 or 2, further comprising: a redundant memory for storing a data corresponding to a disabled memory cell of said memory cell array; and a switch circuit for selecting one of output signals from said shift register and said redundant memory.
Claim 5
Dependent Claim
74 words
A memory apparatus, according to claim 3, further comprising: a selector for storing a data corresponding to said disabled memory cell of said memory cell array, comparing said counted value of said counter with said data corresponding to said disabled memory cell, and supplying a signal to said switching circuit to select an output signal from said redundant memory, when said counted value becomes equal to said data corresponding to said disabled memory cell.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-29 | 1998-02-28 | 1998-08-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-29 | 2002-02-28 | 2002-08-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-29 | 2006-02-28 | 2006-08-30 | $7700.00 | Window Closed / Lapsed |