Variable length shift register

Claim 2

A shift register having a capacity of N stages where N is greater than two comprising: input means and output means; M+N stages of memory means for storing data; readings means for sequentially reading data from said memory means to said output means; and writing means for sequentially writing data from said input means into the N-1 memory stage from a last read memory means; whereby the reading and writing shifts with respect to stationary data in said memory means.

Claim 3

A shift register according to claim 1 wherein said reading means includes means for adjusting N to form a variable length shift register.

Claim 4

A shift register according to claim 1 wherein said reading and writing means includes restarting means for restarting the sequence of reading and writing respectively when the next memory means to be read and written respectively is the M+N+1 stage.

Claim 5

A shift register according to claim 3 wherein said restarting means includes a resettable counter for resettable sequencing said reading means and said writing means.

Claim 6

A shift register according to claim 1 wherein said reading means and said writing means each includes a counter resetting at M+N+1 for restarting the sequencing of said reading and writing means respectively.

Claim 7

A shift register according to claim 1 wherein said memory means is dual port and said reading means and writing means operate simultaneously.

Claim 8

A shift register comprising: input means and output means; N stages of memory means for storing data where N is greater than two; reading means for sequentially reading data from said memory means to said output means; writing means for sequentially writing data from said input means into an adjacent memory means stage prior to a last read memory means; and restarting means for restarting the sequence of reading when the previous memory means stage read from is the Nth stage and restarting the sequence of writing when the previous memory means stage written into is the Nth stage; whereby the reading and writing shifts with respect to stationary data in said memory means.

Claim 9

A shift register comprising: input means and output means; N stages of memory means for storing data where N is greater than two; reading means for sequentially reading data from said memory means to said output means; writing means for sequentially writing data from said input means into an adjacent memory means stage prior to a last read memory means; and restarting means for restarting the sequence of reading when the previous memory means stage read from is the Nth stage and restarting the sequence of writing when the previous memory means stage written into is the Nth stage; whereby the reading and writing shifts with respect to stationary data in said memory means.

Claim 10

A shift register according to claim 7 wherein said restarting means includes a resettable counter for resettable sequencing said reading means and said writing means.

Claim 11

A shift register according to claim 7 wherein said memory means is dual port and said reading means and writing means operate simultaneously.

Claim 12

A shift register according to claim 9 including: a storage means for storing data of said Nth stage; and wherein said writing means writes data into said storage means when said reading means is reading a first stage memory means and said reading means reads data from said storage means when said writing means is writing in an N-1 stage memory means.

Claim 13

A shift register according to claim 9 wherein: adjacent memory means share a common select line which is connected to read select of one memory means and write select of the other memory means; and said reading and writing means are common and select said common select line.

Claim 14

A shift register according to claim 7 including: N+M stage of memory means for storing data; and wherein said restarting means is adjustable for varying the stage at which said sequence is restarted to produce a variable length shift register.

Claim 15

A shift register comprising: input means and output means; N stages of memory means having dual ports for storing data, wherein N is greater than two; a plurality of common select lines, one between each adjacent stage of memory means and connected to a read select of one memory means and a write select of the other memory means; select means for driving one of said select lines to read out data from one memory means to said output means and write data from said input means into an adjacent prior memory means simultaneously; and sequencing means for sequencing said select means from a first stage to an Nth stage and restarting with said first stage; whereby the reading and writing shifts with respect to stationary data in said memory means.

Claim 16

A shift register comprising: input means and output means; N stages of memory means having dual ports for storing data, wherein N is greater than two; a plurality of common select lines, one between each adjacent stage of memory means and connected to a read select of one memory means and a write select of the other memory means; select means for driving one of said select lines to read out data from one memory means to said output means and write data from said input means into an adjacent prior memory means simultaneously; and sequencing means for sequencing said select means from a first stage to an Nth stage and restarting with said first stage; whereby the reading and writing shifts with respect to stationary data in said memory means.

Claim 17

A shift register according to claim 13 wherein said sequencing means includes a resettable counter.

Claim 18

A shift register according to claim 13 including storage means for storing data of said Nth stage; and wherein said select means writes data into said storage means when it drives a select line to read a first stage memory means and reads data from said storage means when it drives a select line to write into an N-1 stage memory means.

Claim 19

A shift register according to claim 13 including: N+M stage of memory means for storing data; and wherein said sequencing means is adjustable for varying the stage at which said sequence is restarted to produce a variable length shift register.