US5342798A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for selective salicidation of source/drain regions of a transistor
Assignee: Philips Semiconductors Inc
•
Filing: 1993-11-23
•
Granted: 1994-08-30
•
Expires: 2013-11-23
Abstract
Abstract Selective salicidation of source/drain regions of a transistor is accomplished by performing an implant into a first plurality of transistor source/drain regions on an integrated circuit. As a result of the implant, doping density of the first plurality of transistor source/drain regions is greater than doping density of a second plurality of transistor source/drain regions on the integrated circuit. The integrated circuit is heated to a heating temperature sufficient to produce oxidation regions immediately over the first plurality of transistor source/drain regions and the second plurality of transistor source/drain regions. The heating temperature is chosen so that the oxidation regions immediately over the first plurality of transistor source/drain regions are thicker than the oxidation regions immediately over the second plurality of transistor source/drain regions. A metal layer is formed over the first plurality of transistor source/drain regions and the second plurality of transistor source/drain regions. The metal layer is annealed at a temperature such that the metal reacts to form metal-silicide over the second plurality of transistor source/drain regions, but not over the first plurality of transistor source/drain regions. The unreacted metal is stripped off over the first plurality of transistor source/drain regions.
Inventors
- 👤 Tiao-Yuan Huang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 00:53
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6306; H10P14/6308; H10P14/6309; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D89/00; H10D89/60; H10D89/601; H10D89/811; H10P14/6322; Y; Y10; Y10S; Y10S148/00; Y10S148/117; Y10S148/147; Y10S438/00; Y10S438/981
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
211 words
A method for selective salicidation of source/drain regions of a transistor, the method comprising the steps of: (a) performing an implant into a first plurality of transistor source/drain regions on an integrated circuit, so that doping density of the first plurality of transistor source/drain regions is greater than doping density of a second plurality of transistor source/drain regions on the integrated circuit; (b) heating the integrated circuit to a heating temperature sufficient to produce oxidation regions immediately over the first plurality of transistor source/drain regions and the second plurality of transistor source/drain regions, the heating temperature being chosen so that the oxidation regions immediately over the first plurality of transistor source/drain regions are thicker than the oxidation regions immediately over the second plurality of transistor source/drain regions; (c) depositing a metal layer on the oxidation regions produced over the first plurality of transistor source/drain regions and the second plurality of transistor source/drain regions; (d) annealing the metal layer deposited in step (c), the annealing being done at a temperature such that the metal reacts to form metal-silicide over the second plurality of transistor source/drain regions, but not over the first plurality of transistor source/drain regions; and, (e) stripping off the unreacted metal from over the first plurality of transistor source/drain regions.
Claim 2
Independent Claim
211 words
A method for selective salicidation of source/drain regions of a transistor, the method comprising the steps of: (a) performing an implant into a first plurality of transistor source/drain regions on an integrated circuit, so that doping density of the first plurality of transistor source/drain regions is greater than doping density of a second plurality of transistor source/drain regions on the integrated circuit; (b) heating the integrated circuit to a heating temperature sufficient to produce oxidation regions immediately over the first plurality of transistor source/drain regions and the second plurality of transistor source/drain regions, the heating temperature being chosen so that the oxidation regions immediately over the first plurality of transistor source/drain regions are thicker than the oxidation regions immediately over the second plurality of transistor source/drain regions; (c) depositing a metal layer on the oxidation regions produced over the first plurality of transistor source/drain regions and the second plurality of transistor source/drain regions; (d) annealing the metal layer deposited in step (c), the annealing being done at a temperature such that the metal reacts to form metal-silicide over the second plurality of transistor source/drain regions, but not over the first plurality of transistor source/drain regions; and, (e) stripping off the unreacted metal from over the first plurality of transistor source/drain regions.
Claim 3
Dependent Claim
34 words
A method as in claim 1 wherein the implant performed in step (a) is an implant of atoms into drain regions of transistors used to provide protection for the integrated circuit against electrostatic discharge.
Claim 4
Dependent Claim
33 words
A method as in claim 1 wherein before step (a), a low doping density implant is performed in the first plurality of transistor source/drain regions and the second plurality of transistor source/drain regions.
Claim 5
Dependent Claim
19 words
A method as in claim 1 wherein the implant performed in step (a) is an n + source/drain implant.
Claim 6
Dependent Claim
19 words
A method as in claim 1 wherein the implant performed in step (a) is a p + source/drain implant.
Claim 7
Dependent Claim
25 words
A method as in claim 1 wherein in step (b), the integrated circuit is in a wet ambient and is heated to 800 degrees Centigrade.
Claim 8
Dependent Claim
48 words
A method as in claim 1 wherein in step (b) a ratio of thickness of the oxidation regions immediately over the first plurality of transistor source/drain regions to thickness of the oxidation regions immediately over the second plurality of transistor source/drain regions is at least two to one.
Claim 9
Dependent Claim
16 words
A method as in claim 1 wherein the metal layer deposited in step (c) is Titanium.
Claim 10
Dependent Claim
25 words
A method as in claim 1 wherein the annealing performed in step (d) is a rapid thermal anneal at 700 degrees centigrade for 15 seconds.
Claim 11
Dependent Claim
25 words
A method as in claim 1 wherein the annealing performed in step (d) is a rapid thermal anneal at 625 degrees centigrade for 60 seconds.
Claim 12
Dependent Claim
31 words
A method as in claim 1, additionally comprising the step of: (f) after step (e), performing a second anneal to fully form metal-silicide over the second plurality of transistor source/drain regions.
Claim 13
Dependent Claim
22 words
A method as in claim 1 additionally comprising the step of: before step (a), forming polycide gates regions for the integrated circuit.
Claim 14
Dependent Claim
31 words
A method as in claim 1 additionally comprising the steps of: before step (a), forming polysilicon gate regions for the integrated circuit, and forming dielectric regions over the polysilicon gate regions.
Claim 15
Dependent Claim
23 words
A method as in claim 13 additionally comprising the step of: before step (c) removing the dielectric regions from the polysilicon gate regions.
Claim 16
Dependent Claim
30 words
A method as in claim 1 wherein before step (a) the following steps are performed: forming gate regions for the integrated circuit; and, forming sidewall spacers around the gate regions.
Claim 17
Dependent Claim
43 words
A method as in claim 15 additionally comprising the step of: after forming the gate regions and before forming the sidewall spacers, performing low doping density implants in the first plurality of transistor source/drain regions and the second plurality of transistor source/drain regions.
Claim 18
Dependent Claim
52 words
A method as in claim 16 wherein after step (e) the following steps are performed: removing the sidewall spacers which are immediately adjacent to the second plurality of transistor source/drain regions; performing source drain implants into the first plurality of transistor source/drain regions and into the second plurality of transistor source/drain regions.
Claim 19
Dependent Claim
48 words
A method as in claim 15 wherein after step (e) the following steps are performed: (f) removing the sidewall spacers from around the gate regions; and, (g) performing low doping density implants in the first plurality of transistor source/drain regions and the second plurality of transistor source/drain regions.
Claim 20
Dependent Claim
30 words
A method as in claim 15 wherein the first plurality of transistor source/drain regions are drain regions of transistors used to provide protection for the integrated circuit against electrostatic discharge.
Claim 21
Dependent Claim
33 words
A method as in claim 15 wherein the first plurality of transistor source/drain regions are drain regions and source regions of transistors used to provide protection for the integrated circuit against electrostatic discharge.
References Cited (Backward Citations)
US4627153A
Cited
US4866002A
Cited
US4874713A
Cited
US5194405A
Cited
US5187122A
Cited
US5262344A
Cited
US5106768A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-29 | 1998-02-28 | 1998-08-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-29 | 2002-02-28 | 2002-08-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-29 | 2006-02-28 | 2006-08-30 | $7700.00 | Window Closed / Lapsed |