US5340751A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a BiMOS device
Assignee: Toshiba Corp
•
Filing: 1991-11-18
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Granted: 1994-08-23
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Expires: 2011-11-18
Abstract
Abstract A method of manufacturing a semiconductor device. A semiconductor substrate is prepared and a gate oxide film is formed on a surface of the semiconductor substrate. The gate oxide film is selectively removed to expose portions of the semiconductor substrate and a first polysilicon layer is formed on a resultant semiconductor structure. Impurities are implanted in the polysilicon layer and a resultant semiconductor structure is annealed to activate the impurities. The first polysilicon layer is patterned to form a base electrode of the bipolar transistor and a gate and/or drain electrode of the MOS transistor. An insulating layer is then formed on a resultant semiconductor structure. Portions of the semiconductor substrate are then selectively exposed and a second polysilicon layer is formed on a resultant semiconductor structure. The second polysilicon layer is then patterned to form an emitter electrode of the bipolar transistor.
Inventors
- 👤 Takeo Maeda
- 👤 Hiroshi Momose
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:03
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/051; H10D84/00; H10D84/40; H10D84/401; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; H10D64/20; H10D64/23; H10D64/231; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S148/00; Y10S148/009
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
144 words
A method of fabricating a semiconductor device including a bipolar transistor and a MOS transistor, the method comprising the steps of: preparing a semiconductor substrate; forming a gate oxide film on a surface of said semiconductor substrate; selectively removing said gate oxide film to expose portions of said semiconductor substrate; forming a first polysilicon layer on a resultant semiconductor structure; implanting impurities in said first polysilicon layer; annealing a resultant semiconductor structure to activate the impurities; patterning said first polysilicon layer to form a base electrode of said bipolar transistor and a gate electrode of said MOS transistor having a same conductivity type; forming an insulating layer on a resultant semiconductor structure; selectively exposing portions of said semiconductor substrate; forming a second polysilicon layer on a resultant semiconductor structure; and patterning said second polysilicon layer to form an emitter electrode of said bipolar transistor.
Claim 2
Independent Claim
144 words
A method of fabricating a semiconductor device including a bipolar transistor and a MOS transistor, the method comprising the steps of: preparing a semiconductor substrate; forming a gate oxide film on a surface of said semiconductor substrate; selectively removing said gate oxide film to expose portions of said semiconductor substrate; forming a first polysilicon layer on a resultant semiconductor structure; implanting impurities in said first polysilicon layer; annealing a resultant semiconductor structure to activate the impurities; patterning said first polysilicon layer to form a base electrode of said bipolar transistor and a gate electrode of said MOS transistor having a same conductivity type; forming an insulating layer on a resultant semiconductor structure; selectively exposing portions of said semiconductor substrate; forming a second polysilicon layer on a resultant semiconductor structure; and patterning said second polysilicon layer to form an emitter electrode of said bipolar transistor.
Claim 3
Dependent Claim
21 words
The method according to claim 1, wherein said gate oxide film is formed to a thickness less than approximately 120 angstroms.
Claim 4
Dependent Claim
21 words
The method according to claim 1, wherein said second polysilicon layer is formed at a temperature less than approximately 600° C.
Claim 5
Dependent Claim
21 words
The method according to claim 1, wherein said first polysilicon layer is formed at a temperature less than approximately 600° C.
References Cited (Backward Citations)
US4589004A
Cited
US4799098A
Cited
US4637125A
Cited
US4914048A
Cited
US4764480A
Cited
US4604790A
Cited
JPS61236153A
Cited
US4806499A
Cited
US4922318A
Cited
JPS62174965A
Cited
US4965216A
Cited
US4784971A
Cited
US4901132A
Cited
JPS6362263A
Cited
US4826783A
Cited
US4902640A
Cited
JPS63287051A
Cited
US4774204A
Cited
US4879255A
Cited
US4980303A
Cited
JPS6457654A
Cited
JPS6481352A
Cited
US4957874A
Cited
US5091322A
Cited
US4960726A
Cited
US5026054A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-22 | 1998-02-21 | 1998-08-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-22 | 2002-02-21 | 2002-08-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-22 | 2006-02-21 | 2006-08-23 | $7700.00 | Window Closed / Lapsed |