Wait state mechanism for a high speed bus which allows the bus to continue running a preset number of cycles after a bus wait is requested

Claim 1

A digital computer apparatus of the type having a computer bus with separate data and address sections and the computer bus having bus cycles of time during which data is driven onto and read from the bus, comprising: a data bus driver module for driving a sequence of data onto the data section of the computer bus and simultaneously storing the driven data in a data relay queue; an address bus driver module for driving a sequence of data onto the address section of the computer bus and simultaneously storing the driven data in an address relay queque; the data bus driver and the address bus driver modules operative to continue to drive the sequence of data on the respective sections of the computer bus simultaneously during a bus wait period associated with a wait command asserted by a bus module; the data bus driver and the address bus driver modules operative to replay on the respective busses, after a determination of the bus wait period, the data stored in the respective replay queues; and data on the computer bus is pipelined such that data driven on the address section of the computer bus precedes, by at least one bus cycle, associated data driven on the data section of the computer bus.